[prci] Provide ibus clock from sbus in BaseSubsystem

chipsalliance · Nov 13, 2020 · 06f39ae · 06f39ae
1 parent e780995
commit 06f39ae
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala
@@ -357,9 +357,6 @@ trait CanHavePeripheryPLIC { this: BaseSubsystem =>
     plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus) := _ }
     plic.intnode :=* ibus.toPLIC
 
-    // TODO: What should be responsible for defining the ibus domain when there's no PLIC?
-    ibus.clockNode := tlbus.fixedClockNode
-
     plic
   }
 }
diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala
@@ -82,6 +82,10 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
   val sbus = tlBusWrapperLocationMap(SBUS)
   tlBusWrapperLocationMap.lift(SBUS).map { _.clockGroupNode := asyncClockGroupsNode }
 
+  // TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding
+  // a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS.
+  ibus.clockNode := sbus.fixedClockNode
+
   // TODO deprecate these public members to see where users are manually hardcoding a particular bus that might actually not exist in a certain dynamic topology
   val pbus = tlBusWrapperLocationMap.lift(PBUS).getOrElse(sbus)
   val fbus = tlBusWrapperLocationMap.lift(FBUS).getOrElse(sbus)