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remove SBT
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sequencer committed Feb 16, 2023
1 parent a880dc8 commit 0b7fef4
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2 changes: 1 addition & 1 deletion CONTRIBUTING.md
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Expand Up @@ -77,6 +77,6 @@ Please see the Github documentation for [Pull Requests](https://help.github.com/

Because Chisel and FIRRTL have mature release processes, Rocket Chip uses the published artifacts.

To bump the published dependencies, bump the versions at the top of the SBT build file: [build.sbt](build.sbt).
To bump the published dependencies, bump the versions at the top of the Mill build file: [build.sc](build.sc).
Typically, the SBT dependency will only list a version for Chisel 3 which itself depends on FIRRTL.

10 changes: 4 additions & 6 deletions Makefrag
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Expand Up @@ -25,7 +25,7 @@ EMPTY :=
SPACE := $(EMPTY) $(EMPTY)
COMMA := ,

SBT ?= java -Xmx$(JVM_MEMORY) -Xss8M -jar $(base_dir)/sbt-launch.jar
MILL ?= mill
SHELL := /bin/bash

FIRRTL_TRANSFORMS := \
Expand All @@ -37,16 +37,14 @@ JAVA ?= java -Xmx$(JVM_MEMORY) -Xss8M
FIRRTL ?= $(JAVA) -cp $(ROCKET_CHIP_JAR) firrtl.stage.FirrtlMain
GENERATOR ?= $(JAVA) -cp $(ROCKET_CHIP_JAR) $(PROJECT).Generator

# Extracting this information from SBT would be more robust
# api-config-chipsalliance does not use standard SBT src/main/scala, but has no resources
scala_srcs := $(shell find $(base_dir) -name "*.scala" -o -name "*.sbt")
scala_srcs := $(shell find $(base_dir) -name "*.scala" -o -name "*.sc")
resource_dirs := $(shell find $(base_dir) -type d -path "*/src/main/resources")
resources := $(foreach d,$(resource_dirs),$(shell find $(d) -type f))
all_srcs := $(scala_srcs) $(resources)

ROCKET_CHIP_JAR := $(base_dir)/rocketchip.jar
ROCKET_CHIP_JAR := $(base_dir)/out/rocketchip/assembly.dest/out.jar
$(ROCKET_CHIP_JAR): $(all_srcs)
cd $(base_dir) && $(SBT) assembly
cd $(base_dir) && $(MILL) rocketchip.assembly

rc_resource_dir := $(base_dir)/src/main/resources
csrc := $(rc_resource_dir)/csrc
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25 changes: 6 additions & 19 deletions README.md
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Expand Up @@ -94,20 +94,6 @@ To generate FPGA- or VLSI-synthesizable Verilog (output will be in `vsim/generat
$ cd vsim
$ make verilog

To run the Scala tests (`sbt test`) or linter (`sbt scalafix`):

$ cd regression

# Scala tests
$ make scalatest SUITE=foo

# Scala linter, automatically modifying files to correct issues
$ make scalafix SUITE=foo

# Scala linter, only printing out issues
$ make scalafix-check SUITE=foo


### Keeping Your Repo Up-to-Date

If you are trying to keep your repo up to date with this GitHub repo,
Expand Down Expand Up @@ -229,8 +215,6 @@ C sources for use with Verilator simulation.
Documentation, tutorials, etc for specific parts of the codebase.
* **emulator**
Directory in which Verilator simulations are compiled and run.
* **project**
Directory used by SBT for Scala compilation and build.
* **regression**
Defines continuous integration and nightly regression suites.
* **scripts**
Expand Down Expand Up @@ -696,10 +680,13 @@ Further information about GDB debugging is available [here](https://sourceware.o

## <a name="ide"></a> Building Rocket Chip with an IDE

The Rocket Chip Scala build uses the standard Scala build tool SBT.
The Rocket Chip Scala build uses [mill](https://github.com/com-lihaoyi/mill) as build tool.
IDEs like [IntelliJ](https://www.jetbrains.com/idea/) and [VSCode](https://code.visualstudio.com/)
are popular in the Scala community and work with Rocket Chip.
To use one of these IDEs, there is one minor peculiarity of the Rocket Chip build that must be addressed.
are popular in the Scala community and work with Rocket Chip. Use:
```
mill mill.bsp.BSP/install
```
to use one of these IDEs, there is one minor peculiarity of the Rocket Chip build that must be addressed.

## <a name="contributors"></a> Contributors

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121 changes: 0 additions & 121 deletions build.sbt

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1 change: 0 additions & 1 deletion project/.gitignore

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1 change: 0 additions & 1 deletion project/build.properties

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21 changes: 0 additions & 21 deletions project/plugins.sbt

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16 changes: 0 additions & 16 deletions regression/Makefile
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Expand Up @@ -335,19 +335,3 @@ emulator-jtag-dtm-tests-64 : $(EMULATOR_JTAG_DTM_64_TEST_STAMPS)
# Targets for JTAG DTM full-chain simulation
vsim-jtag-dtm-regression: vsim-jtag-dtm-tests-32 vsim-jtag-dtm-tests-64
emulator-jtag-dtm-regression: emulator-jtag-dtm-tests-32 emulator-jtag-dtm-tests-64

# Target to run Scalatest regressions 'sbt test'
.PHONY: scalatest
scalatest: stamps/other-submodules.stamp $(all_srcs)
(cd $(base_dir) && $(SBT) $(SBT_OPTS) test)

# Target to run Scalafix 'sbt scalafix'
.PHONY: scalafix
scalafix: stamps/other-submodules.stamp $(all_srcs)
(cd $(base_dir) && $(SBT) $(SBT_OPTS) scalafix)

# Target to run Scalafix 'sbt scalafix --check', which will not actually modify
# Scala files.
.PHONY: scalafix-check
scalafix-check: stamps/other-submodules.stamp $(all_srcs)
(cd $(base_dir) && $(SBT) $(SBT_OPTS) 'scalafix --check')
6 changes: 0 additions & 6 deletions regression/run-test-bucket
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Expand Up @@ -70,12 +70,6 @@ case "${bucket_number}" in
7)
make emulator-ndebug -C regression SUITE=Miscellaneous JVM_MEMORY=3G
;;
8)
make scalatest -C regression SUITE=foo JVM_MEMORY=8G
;;
9)
make scalafix-check -C regression SUITE=foo JVM_MEMORY=8G
;;

-h|--help)
print_usage
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