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Fix shared FPU for divSqrt ops
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jerryz123 committed Jan 29, 2024
1 parent 0292f13 commit 0bff786
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/main/scala/tile/FPU.scala
Original file line number Diff line number Diff line change
Expand Up @@ -972,7 +972,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}

when (wb_cp && wen(0)) {
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
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