Use unmodified, possibly async reset for notification ports

src/main/scala/subsystem/HasTiles.scala

@@ -348,6 +348,10 @@ trait CanAttachTile {
     domain {
       domain.clockSinkNode := crossingParams.injectClockNode(context) := domain.clockNode
     } := clockSource
+
+    domain {
+      domain.tile.externalClockSinkNode
+    } := clockSource
   }
 }
 

src/main/scala/tile/BaseTile.scala

@@ -11,6 +11,7 @@ import freechips.rocketchip.diplomaticobjectmodel.{HasLogicalTreeNode}
 import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{GenericLogicalTreeNode, LogicalTreeNode}
 
 import freechips.rocketchip.interrupts._
+import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
@@ -282,6 +283,10 @@ abstract class BaseTile private (val crossing: ClockCrossingType, q: Parameters)
   val bpwatchNode: BundleBridgeOutwardNode[Vec[BPWatch]] =
     BundleBridgeNameNode("bpwatch") :*= bpwatchNexusNode := bpwatchSourceNode
 
+  /** Node to receive raw core_clock and core_reset */
+  val externalClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters()))
+  def rawReset = externalClockSinkNode.in.head._1.reset
+
   /** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external masters. */
   def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int) {
     DisableMonitors { implicit p =>

src/main/scala/tile/Interrupts.scala

@@ -82,7 +82,7 @@ trait SourcesExternalNotifications { this: BaseTile =>
 
   def reportHalt(could_halt: Option[Bool]) {
     val (halt_and_catch_fire, _) = haltNode.out(0)
-    halt_and_catch_fire(0) := could_halt.map(RegEnable(true.B, false.B, _)).getOrElse(false.B)
+    halt_and_catch_fire(0) := could_halt.map(h => RegEnable(true.B, false.B, BlockDuringReset(h))).getOrElse(false.B)
   }
 
   def reportHalt(errors: Seq[CanHaveErrors]) {
@@ -116,6 +116,6 @@ trait SourcesExternalNotifications { this: BaseTile =>
 
   def reportWFI(could_wfi: Option[Bool]) {
     val (wfi, _) = wfiNode.out(0)
-    wfi(0) := could_wfi.map(RegNext(_, init=false.B)).getOrElse(false.B)
+    wfi(0) := could_wfi.map(w => RegNext(BlockDuringReset(w), init=false.B)).getOrElse(false.B)
   }
 }

src/main/scala/tile/RocketTile.scala

@@ -4,6 +4,7 @@
 package freechips.rocketchip.tile
 
 import Chisel._
+import chisel3.withReset
 import freechips.rocketchip.config._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
@@ -136,17 +137,19 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
 
   val core = Module(new Rocket(outer)(outer.p))
 
-  // Report unrecoverable error conditions; for now the only cause is cache ECC errors
-  outer.reportHalt(List(outer.dcache.module.io.errors))
+  withReset(outer.rawReset) {   // use unmodified reset for notification ports
+    // Report unrecoverable error conditions; for now the only cause is cache ECC errors
+    outer.reportHalt(List(outer.dcache.module.io.errors))
 
-  // Report when the tile has ceased to retire instructions; for now the only cause is clock gating
-  outer.reportCease(outer.rocketParams.core.clockGate.option(
-    !outer.dcache.module.io.cpu.clock_enabled &&
-    !outer.frontend.module.io.cpu.clock_enabled &&
-    !ptw.io.dpath.clock_enabled &&
-    core.io.cease))
+    // Report when the tile has ceased to retire instructions; for now the only cause is clock gating
+    outer.reportCease(outer.rocketParams.core.clockGate.option(
+      !outer.dcache.module.io.cpu.clock_enabled &&
+      !outer.frontend.module.io.cpu.clock_enabled &&
+      !ptw.io.dpath.clock_enabled &&
+      core.io.cease))
 
-  outer.reportWFI(Some(core.io.wfi))
+    outer.reportWFI(Some(core.io.wfi))
+  }
 
   outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector