CSR Decode: Expanded Instruction for c.ebreak

chipsalliance · Jun 9, 2021 · 403ce8a · 403ce8a
1 parent 80d3fec
commit 403ce8a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -704,7 +704,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
 
   // hook up control/status regfile
   csr.io.ungated_clock := clock
-  csr.io.decode(0).inst := id_raw_inst(0)
+  csr.io.decode(0).inst := id_inst(0)
   csr.io.exception := wb_xcpt
   csr.io.cause := wb_cause
   csr.io.retire := wb_valid