Merge remote-tracking branch 'origin/dev' into ifv

.gitmodules

@@ -7,3 +7,7 @@
 [submodule "dependencies/chisel"]
 	path = dependencies/chisel
 	url = https://github.com/chipsalliance/chisel.git
+[submodule "dependencies/diplomacy"]
+	path = dependencies/diplomacy
+	url = https://github.com/chipsalliance/diplomacy.git
+	branch = master

build.sc

@@ -4,6 +4,7 @@ import mill.scalalib.publish._
 import coursier.maven.MavenRepository
 import $file.dependencies.hardfloat.common
 import $file.dependencies.cde.common
+import $file.dependencies.diplomacy.common
 import $file.dependencies.chisel.build
 import $file.common
 
@@ -18,6 +19,7 @@ object v {
   val mainargs = ivy"com.lihaoyi::mainargs:0.5.0"
   val json4sJackson = ivy"org.json4s::json4s-jackson:4.0.5"
   val scalaReflect = ivy"org.scala-lang:scala-reflect:${scala}"
+  val sourcecode = ivy"com.lihaoyi::sourcecode:0.3.1"
   val sonatypesSnapshots = Seq(
     MavenRepository("https://s01.oss.sonatype.org/content/repositories/snapshots")
   )
@@ -79,6 +81,31 @@ trait CDE
   override def millSourcePath = os.pwd / "dependencies" / "cde" / "cde"
 }
 
+object diplomacy extends mill.define.Cross[Diplomacy](v.chiselCrossVersions.keys.toSeq)
+
+trait Diplomacy
+    extends millbuild.dependencies.diplomacy.common.DiplomacyModule
+    with RocketChipPublishModule
+    with Cross.Module[String] {
+
+  override def scalaVersion: T[String] = T(v.scala)
+
+  override def millSourcePath = os.pwd / "dependencies" / "diplomacy" / "diplomacy"
+
+  // dont use chisel from source
+  def chiselModule    = None
+  def chiselPluginJar = None
+
+  // use chisel from ivy
+  def chiselIvy       = Some(v.chiselCrossVersions(crossValue)._1)
+  def chiselPluginIvy = Some(v.chiselCrossVersions(crossValue)._2)
+
+  // use CDE from source until published to sonatype
+  def cdeModule = cde
+
+  def sourcecodeIvy = v.sourcecode
+}
+
 object rocketchip extends Cross[RocketChip](v.chiselCrossVersions.keys.toSeq)
 
 trait RocketChip
@@ -104,6 +131,10 @@ trait RocketChip
 
   def cdeModule = cde
 
+  def diplomacyModule = diplomacy(crossValue)
+
+  def diplomacyIvy = None
+
   def mainargsIvy = v.mainargs
 
   def json4sJacksonIvy = v.json4sJackson
@@ -127,7 +158,6 @@ trait RocketChipPublishModule
   override def publishVersion: T[String] = T("1.6-SNAPSHOT")
 }
 
-
 // Tests
 trait Emulator extends Cross.Module2[String, String] {
   val top: String = crossValue

common.sc

@@ -42,19 +42,18 @@ trait RocketChipModule
   // should be hardfloat/common.sc#HardfloatModule
   def hardfloatModule: ScalaModule
 
-  // should be cde/common.sc#CDEModule
-  def cdeModule: ScalaModule
+  def diplomacyModule: ScalaModule
 
   def mainargsIvy: Dep
 
   def json4sJacksonIvy: Dep
 
-  override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, cdeModule)
+  override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, diplomacyModule)
 
   override def ivyDeps = T(
     super.ivyDeps() ++ Agg(
       mainargsIvy,
-      json4sJacksonIvy
+      json4sJacksonIvy,
     )
   )
 }

src/main/scala/amba/axi4/Xbar.scala

@@ -85,7 +85,12 @@ class AXI4Xbar(
     // Transform input bundles
     val in = Wire(Vec(io_in.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until in.size) {
-      in(i).squeezeAll :<>= io_in(i).squeezeAll
+      in(i).aw.bits.user := DontCare
+      in(i).aw.bits.echo := DontCare
+      in(i).ar.bits.user := DontCare
+      in(i).ar.bits.echo := DontCare
+      in(i).w.bits.user := DontCare
+      in(i).squeezeAll.waiveAll :<>= io_in(i).squeezeAll.waiveAll
 
       // Handle size = 1 gracefully (Chisel3 empty range is broken)
       def trim(id: UInt, size: Int) = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
@@ -168,7 +173,9 @@ class AXI4Xbar(
     // Transform output bundles
     val out = Wire(Vec(io_out.size, new AXI4Bundle(wide_bundle)))
     for (i <- 0 until out.size) {
-      io_out(i).squeezeAll :<>= out(i).squeezeAll
+      out(i).b.bits.user := DontCare
+      out(i).r.bits.user := DontCare
+      io_out(i).squeezeAll.waiveAll :<>= out(i).squeezeAll.waiveAll
 
       if (io_in.size > 1) {
         // Block AW if we cannot record the W source

src/main/scala/aop/package.scala

@@ -0,0 +1,6 @@
+package freechips.rocketchip
+
+object aop {
+  @deprecated("aop has moved to the standalone diplomacy library.", "rocketchip 2.0.0")
+  val Select = _root_.org.chipsalliance.diplomacy.aop.Select
+}

src/main/scala/devices/tilelink/CLINT.scala

@@ -105,7 +105,7 @@ trait CanHavePeripheryCLINT { this: BaseSubsystem =>
   val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params =>
     val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
     val clintDomainWrapper = tlbus.generateSynchronousDomain.suggestName("clint_domain")
-    val clint = clintDomainWrapper { LazyModule(new CLINT(params, cbus.beatBytes)) }
+    val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) }
     clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ } }
     val clintTick = clintDomainWrapper { InModuleBody {
       val tick = IO(Input(Bool()))