Add time to TraceBundle

chipsalliance · May 10, 2023 · 57af718 · 57af718
1 parent 85aca71
commit 57af718
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Showing 2 changed files with 2 additions and 0 deletions.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -813,6 +813,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr)
   csr.io.rw.wdata := wb_reg_wdata
   io.trace.insns := csr.io.trace
+  io.trace.time := csr.io.time
   for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) {
     iobpw.valid(0) := wphit
     iobpw.action := bp.control.action

diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
@@ -153,6 +153,7 @@ class CoreInterrupts(implicit p: Parameters) extends TileInterrupts()(p) {
 // This is a raw commit trace from the core, not the TraceCoreInterface
 class TraceBundle(implicit val p: Parameters) extends Bundle with HasCoreParameters {
   val insns = Vec(coreParams.retireWidth, new TracedInstruction)
+  val time = UInt(64.W)
 }
 
 trait HasCoreIO extends HasTileParameters {