Port AMBA to standalone diplomacy

Updates AMBA to use standalone diplomacy module directly. Fixes a small issue with builds using chisel source for diplomacy module.
chipsalliance · Mar 18, 2024 · 6036838 · 6036838
1 parent f228714
commit 6036838
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Showing 42 changed files with 252 additions and 109 deletions.
diff --git a/build.sc b/build.sc
@@ -93,12 +93,12 @@ trait Diplomacy
   override def millSourcePath = os.pwd / "dependencies" / "diplomacy" / "diplomacy"
 
   // dont use chisel from source
-  def chiselModule    = None
-  def chiselPluginJar = None
+  def chiselModule = Option.when(crossValue == "source")(chisel)
+  def chiselPluginJar = T(Option.when(crossValue == "source")(chisel.pluginModule.jar()))
 
   // use chisel from ivy
-  def chiselIvy       = Some(v.chiselCrossVersions(crossValue)._1)
-  def chiselPluginIvy = Some(v.chiselCrossVersions(crossValue)._2)
+  def chiselIvy = Option.when(crossValue != "source")(v.chiselCrossVersions(crossValue)._1)
+  def chiselPluginIvy = Option.when(crossValue != "source")(v.chiselCrossVersions(crossValue)._2)
 
   // use CDE from source until published to sonatype
   def cdeModule = cde

diff --git a/src/main/scala/amba/ahb/AHBLite.scala b/src/main/scala/amba/ahb/AHBLite.scala
@@ -4,7 +4,7 @@ package freechips.rocketchip.amba.ahb
 
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
 
 class AHBLite()(implicit p: Parameters) extends LazyModule {
   val node = AHBMasterAdapterNode(

diff --git a/src/main/scala/amba/ahb/Nodes.scala b/src/main/scala/amba/ahb/Nodes.scala
@@ -4,8 +4,11 @@ package freechips.rocketchip.amba.ahb
 
 import chisel3._
 import chisel3.experimental.SourceInfo
+
 import org.chipsalliance.cde.config.{Parameters, Field}
-import freechips.rocketchip.diplomacy._
+
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp, RenderedEdge, OutwardNode, InwardNode, SourceNode, SinkNode, IdentityNode, AdapterNode, MixedNexusNode, NexusNode}
 
 case object AHBSlaveMonitorBuilder extends Field[AHBSlaveMonitorArgs => AHBSlaveMonitorBase]
 

diff --git a/src/main/scala/amba/ahb/Parameters.scala b/src/main/scala/amba/ahb/Parameters.scala
@@ -2,11 +2,16 @@
 
 package freechips.rocketchip.amba.ahb
 
-import chisel3.util._
 import chisel3.experimental.SourceInfo
+import chisel3.util._
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util._
+
+import org.chipsalliance.diplomacy.nodes.BaseNode
+
+import freechips.rocketchip.diplomacy.{AddressSet, Resource, RegionType, TransferSizes, Device, ResourceAddress, ResourcePermissions}
+import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase}
+
 import scala.math.{max, min}
 
 case class AHBSlaveParameters(

diff --git a/src/main/scala/amba/ahb/RegisterRouter.scala b/src/main/scala/amba/ahb/RegisterRouter.scala
@@ -3,12 +3,18 @@
 package freechips.rocketchip.amba.ahb
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.{log2Up, log2Ceil, Decoupled}
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.regmapper._
+
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.nodes.{SinkNode}
+
+import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
+import freechips.rocketchip.regmapper.{RegMapperParams, RegField, RegMapperInput, RegisterRouter, RegMapper}
 import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
-import freechips.rocketchip.util._
+import freechips.rocketchip.util.MaskGen
+
 import scala.math.min
 
 case class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)

diff --git a/src/main/scala/amba/ahb/SRAM.scala b/src/main/scala/amba/ahb/SRAM.scala
@@ -5,9 +5,11 @@ package freechips.rocketchip.amba.ahb
 import chisel3._
 import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util._
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType, TransferSizes}
 import freechips.rocketchip.tilelink.LFSRNoiseMaker
+import freechips.rocketchip.util.{MaskGen, DataToAugmentedData, SeqMemToAugmentedSeqMem, PlusArg}
 
 class AHBRAM(
     address: AddressSet,

diff --git a/src/main/scala/amba/ahb/Test.scala b/src/main/scala/amba/ahb/Test.scala
@@ -3,12 +3,16 @@
 package freechips.rocketchip.amba.ahb
 
 import chisel3._
+
 import org.chipsalliance.cde.config.Parameters
+
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp, SimpleLazyModule}
+
 import freechips.rocketchip.devices.tilelink.TLTestRAM
-import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
 import freechips.rocketchip.regmapper.{RRTest0, RRTest1}
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.unittest._
+import freechips.rocketchip.tilelink.{TLFuzzer, TLRAMModel, TLToAHB, TLDelayer, TLBuffer, TLErrorEvaluator, TLFragmenter}
+import freechips.rocketchip.unittest.{UnitTestModule, UnitTest}
 
 class AHBRRTest0(address: BigInt)(implicit p: Parameters)
   extends RRTest0(address)

diff --git a/src/main/scala/amba/ahb/ToTL.scala b/src/main/scala/amba/ahb/ToTL.scala
@@ -4,11 +4,17 @@ package freechips.rocketchip.amba.ahb
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.amba._
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
+
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.nodes.{MixedAdapterNode}
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.amba.{AMBAProtField, AMBAProt}
+import freechips.rocketchip.diplomacy.TransferSizes
+import freechips.rocketchip.tilelink.{TLImp, TLMasterPortParameters, TLMessages, TLMasterParameters, TLMasterToSlaveTransferSizes}
+import freechips.rocketchip.util.{BundleMap, MaskGen, DataToAugmentedData}
 
 case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHBImpSlave, TLImp)(
   dFn = { case mp =>

diff --git a/src/main/scala/amba/ahb/Xbar.scala b/src/main/scala/amba/ahb/Xbar.scala
@@ -3,10 +3,14 @@
 package freechips.rocketchip.amba.ahb
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.Mux1H
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util._
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.AddressDecoder
+import freechips.rocketchip.util.BundleField
+
 
 class AHBFanout()(implicit p: Parameters) extends LazyModule {
   val node = new AHBFanoutNode(

diff --git a/src/main/scala/amba/ahb/package.scala b/src/main/scala/amba/ahb/package.scala
@@ -2,7 +2,7 @@
 
 package freechips.rocketchip.amba
 
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, SimpleNodeHandle}
 
 package object ahb
 {

diff --git a/src/main/scala/amba/apb/Nodes.scala b/src/main/scala/amba/apb/Nodes.scala
@@ -4,8 +4,11 @@ package freechips.rocketchip.amba.apb
 
 import chisel3._
 import chisel3.experimental.SourceInfo
+
 import org.chipsalliance.cde.config.{Parameters, Field}
-import freechips.rocketchip.diplomacy._
+
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp,RenderedEdge, InwardNode, OutwardNode, SourceNode, SinkNode, NexusNode, IdentityNode}
 
 case object APBMonitorBuilder extends Field[APBMonitorArgs => APBMonitorBase]
 

diff --git a/src/main/scala/amba/apb/Parameters.scala b/src/main/scala/amba/apb/Parameters.scala
@@ -2,11 +2,17 @@
 
 package freechips.rocketchip.amba.apb
 
-import chisel3.util._
+import chisel3.util.{isPow2, log2Up}
 import chisel3.experimental.SourceInfo
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util._
+
+import org.chipsalliance.diplomacy.nodes.BaseNode
+
+import freechips.rocketchip.diplomacy.{AddressSet, Resource, Device, RegionType, ResourceAddress, ResourcePermissions}
+
+import freechips.rocketchip.util.{BundleField, BundleKeyBase, BundleFieldBase}
+
 import scala.math.max
 
 case class APBSlaveParameters(

diff --git a/src/main/scala/amba/apb/RegisterRouter.scala b/src/main/scala/amba/apb/RegisterRouter.scala
@@ -3,10 +3,15 @@
 package freechips.rocketchip.amba.apb
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.{Decoupled, log2Up, log2Ceil}
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.regmapper._
+
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.nodes.SinkNode
+
+import freechips.rocketchip.diplomacy.AddressSet
+import freechips.rocketchip.regmapper.{RegField, RegMapperParams, RegMapperInput, RegMapper, RegisterRouter}
 import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
 
 case class APBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)

diff --git a/src/main/scala/amba/apb/SRAM.scala b/src/main/scala/amba/apb/SRAM.scala
@@ -3,11 +3,15 @@
 package freechips.rocketchip.amba.apb
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.{Cat, log2Ceil, RegEnable}
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util._
+
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType}
 import freechips.rocketchip.tilelink.LFSRNoiseMaker
+import freechips.rocketchip.util.SeqMemToAugmentedSeqMem
 
 class APBRAM(
     address: AddressSet,

diff --git a/src/main/scala/amba/apb/Test.scala b/src/main/scala/amba/apb/Test.scala
@@ -3,10 +3,14 @@
 package freechips.rocketchip.amba.apb
 
 import chisel3._
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.{BufferParams, AddressSet}
 import freechips.rocketchip.regmapper.{RRTest0, RRTest1}
-import freechips.rocketchip.tilelink._
+import freechips.rocketchip.tilelink.{TLFuzzer, TLRAMModel, TLToAPB, TLDelayer, TLBuffer, TLFragmenter}
 import freechips.rocketchip.unittest._
 
 class APBRRTest0(address: BigInt)(implicit p: Parameters) 

diff --git a/src/main/scala/amba/apb/ToTL.scala b/src/main/scala/amba/apb/ToTL.scala
@@ -4,11 +4,16 @@ package freechips.rocketchip.amba.apb
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.amba._
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
+
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.nodes.{MixedAdapterNode}
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.amba.{AMBAProt, AMBAProtField}
+import freechips.rocketchip.diplomacy.TransferSizes
+import freechips.rocketchip.tilelink.{TLImp, TLMessages, TLMasterPortParameters, TLMasterParameters}
 
 case class APBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(APBImp, TLImp)(
   dFn = { mp =>

diff --git a/src/main/scala/amba/apb/Xbar.scala b/src/main/scala/amba/apb/Xbar.scala
@@ -3,10 +3,14 @@
 package freechips.rocketchip.amba.apb
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.Mux1H
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util._
+
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.AddressDecoder
+import freechips.rocketchip.util.BundleField
 
 class APBFanout()(implicit p: Parameters) extends LazyModule {
   val node = new APBNexusNode(

diff --git a/src/main/scala/amba/apb/package.scala b/src/main/scala/amba/apb/package.scala
@@ -2,7 +2,7 @@
 
 package freechips.rocketchip.amba
 
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, SimpleNodeHandle}
 
 package object apb
 {

diff --git a/src/main/scala/amba/axi4/AsyncCrossing.scala b/src/main/scala/amba/axi4/AsyncCrossing.scala
@@ -3,11 +3,16 @@
 package freechips.rocketchip.amba.axi4
 
 import chisel3._
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
+
+import org.chipsalliance.diplomacy.nodes.{NodeHandle}
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.{AddressSet, AsynchronousCrossing}
+import freechips.rocketchip.tilelink.{TLRAMModel, TLFuzzer, TLToAXI4}
 import freechips.rocketchip.subsystem.CrossingWrapper
-import freechips.rocketchip.util._
+import freechips.rocketchip.util.{ToAsyncBundle, FromAsyncBundle, AsyncQueueParams, Pow2ClockDivider}
 
 /**
   * Source(Master) side for AXI4 crossing clock domain

diff --git a/src/main/scala/amba/axi4/Buffer.scala b/src/main/scala/amba/axi4/Buffer.scala
@@ -4,8 +4,13 @@ package freechips.rocketchip.amba.axi4
 
 import chisel3._
 import chisel3.util.{Queue, IrrevocableIO}
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.BufferParams
+
 import scala.math.min
 
 /**

diff --git a/src/main/scala/amba/axi4/Credited.scala b/src/main/scala/amba/axi4/Credited.scala
@@ -3,10 +3,14 @@
 package freechips.rocketchip.amba.axi4
 
 import chisel3._
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
+
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.{AddressSet, CreditedCrossing}
 import freechips.rocketchip.subsystem.CrossingWrapper
+import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 
 class AXI4CreditedBuffer(delay: AXI4CreditedDelay)(implicit p: Parameters) extends LazyModule

diff --git a/src/main/scala/amba/axi4/CrossingHelper.scala b/src/main/scala/amba/axi4/CrossingHelper.scala
@@ -3,7 +3,9 @@
 package freechips.rocketchip.amba.axi4
 
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule.{LazyScope}
+
+import freechips.rocketchip.diplomacy.{CrossingType, ClockCrossingType, NoCrossing, AsynchronousCrossing, RationalCrossing, SynchronousCrossing, CreditedCrossing}
 import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing}
 
 trait AXI4OutwardCrossingHelper {

diff --git a/src/main/scala/amba/axi4/Deinterleaver.scala b/src/main/scala/amba/axi4/Deinterleaver.scala
@@ -5,8 +5,12 @@ package freechips.rocketchip.amba.axi4
 import chisel3._
 import chisel3.util.{Cat, isPow2, log2Ceil, ReadyValidIO,
   log2Up, OHToUInt, Queue, QueueIO, UIntToOH}
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
+import freechips.rocketchip.diplomacy.{BufferParams, TransferSizes}
 import freechips.rocketchip.util.leftOR
 
 /** This adapter deinterleaves read responses on the R channel.

diff --git a/src/main/scala/amba/axi4/Delayer.scala b/src/main/scala/amba/axi4/Delayer.scala
@@ -3,9 +3,12 @@
 package freechips.rocketchip.amba.axi4
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.IrrevocableIO
+
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
+
 import freechips.rocketchip.tilelink.LFSRNoiseMaker
 
 /**