TLB: correctly propagate LSBs of GPA

src/main/resources/vsrc/RoccBlackBox.v

@@ -92,6 +92,7 @@ module RoccBlackBox
     input rocc_mem_s2_uncached,
     input [paddrBits-1:0] rocc_mem_s2_paddr,
     input [vaddrBitsExtended-1:0] rocc_mem_s2_gpa,
+    input rocc_mem_s2_gpa_is_pte,
     input rocc_mem_resp_valid,
     input [coreMaxAddrBits-1:0] rocc_mem_resp_bits_addr,
     input [dcacheReqTagBits-1:0] rocc_mem_resp_bits_tag,

src/main/scala/rocket/DCache.scala

@@ -895,6 +895,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   io.cpu.s2_uncached := s2_uncached && !s2_hit
   io.cpu.s2_paddr := s2_req.addr
   io.cpu.s2_gpa := s2_tlb_xcpt.gpa
+  io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte
 
   // report whether there are any outstanding accesses.  disregard any
   // slave-port accesses, since they don't affect local memory ordering.

src/main/scala/rocket/HellaCache.scala

@@ -177,6 +177,7 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
   val replay_next = Bool(INPUT)
   val s2_xcpt = (new HellaCacheExceptions).asInput
   val s2_gpa = UInt(vaddrBitsExtended.W).asInput
+  val s2_gpa_is_pte = Bool(INPUT)
   val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Decoupled(new HellaCacheResp).flip)
   val ordered = Bool(INPUT)
   val perf = new HellaCachePerfEvents().asInput

src/main/scala/rocket/HellaCacheArbiter.scala

@@ -60,6 +60,7 @@ class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
       resp.valid := io.mem.resp.valid && tag_hit
       io.requestor(i).s2_xcpt := io.mem.s2_xcpt
       io.requestor(i).s2_gpa := io.mem.s2_gpa
+      io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte
       io.requestor(i).ordered := io.mem.ordered
       io.requestor(i).perf := io.mem.perf
       io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === UInt(i)

src/main/scala/rocket/TLB.scala

@@ -53,6 +53,7 @@ class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
   val miss = Bool()
   val paddr = UInt(width = paddrBits)
   val gpa = UInt(vaddrBitsExtended.W)
+  val gpa_is_pte = Bool()
   val pf = new TLBExceptions
   val gf = new TLBExceptions
   val ae = new TLBExceptions
@@ -431,9 +432,10 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
   io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint)
   io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits
   io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
+  io.resp.gpa_is_pte := vstage1_en && r_gpa_gf
   io.resp.gpa := {
     val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits)
-    val offset = Mux(!vstage1_en || !r_gpa_gf, io.req.bits.vaddr(pgIdxBits-1, 0), r_gpa(pgIdxBits-1, 0))
+    val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0))
     Cat(page, offset)
   }