Merge pull request #3473 from chipsalliance/no_ext_int_fix

fix PLIC 0-bit connection
chipsalliance · Aug 18, 2023 · 7681e28 · 7681e28
2 parents 52e57f1 + d28a3a3
commit 7681e28
Showing 1 changed file with 8 additions and 6 deletions.
diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala
@@ -179,12 +179,14 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
 
     val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))
     val pendingUInt = Cat(pending.reverse)
-    for (hart <- 0 until nHarts) {
-      val fanin = Module(new PLICFanIn(nDevices, prioBits))
-      fanin.io.prio := priority
-      fanin.io.ip   := enableVec(hart) & pendingUInt
-      maxDevs(hart) := fanin.io.dev
-      harts(hart)   := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)
+    if(nDevices > 0) {
+      for (hart <- 0 until nHarts) {
+        val fanin = Module(new PLICFanIn(nDevices, prioBits))
+        fanin.io.prio := priority
+        fanin.io.ip := enableVec(hart) & pendingUInt
+        maxDevs(hart) := fanin.io.dev
+        harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)
+      }
     }
 
     // Priority registers are 32-bit aligned so treat each as its own group.