Merge pull request #3307 from chipsalliance/mergify/bp/master/pr-3304

Change CharCountRoCC Example to use dcacheParams (backport #3304)
chipsalliance · Mar 23, 2023 · a4e718f · a4e718f
2 parents e4e8aaf + b7dbf26
commit a4e718f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/tile/LazyRoCC.scala b/src/main/scala/tile/LazyRoCC.scala
@@ -243,7 +243,7 @@ class  CharacterCountExample(opcodes: OpcodeSet)(implicit p: Parameters) extends
 class CharacterCountExampleModuleImp(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)
   with HasCoreParameters
   with HasL1CacheParameters {
-  val cacheParams = tileParams.icache.get
+  val cacheParams = tileParams.dcache.get
 
   private val blockOffset = blockOffBits
   private val beatOffset = log2Up(cacheDataBits/8)