Move dts/resources to new resources subpackage

chipsalliance · Jun 6, 2024 · a73b797 · a73b797
1 parent aea0064
commit a73b797
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Showing 51 changed files with 144 additions and 102 deletions.
diff --git a/src/main/scala/amba/ahb/Parameters.scala b/src/main/scala/amba/ahb/Parameters.scala
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config.Parameters
 
 import org.chipsalliance.diplomacy.nodes.BaseNode
 
-import freechips.rocketchip.diplomacy.{AddressSet, Resource, RegionType, TransferSizes, Device, ResourceAddress, ResourcePermissions}
+import freechips.rocketchip.resources.{Resource, Device, ResourceAddress, ResourcePermissions}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
 import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase}
 
 import scala.math.{max, min}

diff --git a/src/main/scala/amba/ahb/SRAM.scala b/src/main/scala/amba/ahb/SRAM.scala
@@ -7,7 +7,8 @@ import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
 
-import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType, TransferSizes}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
+import freechips.rocketchip.resources.{DiplomaticSRAM, HasJustOneSeqMem}
 import freechips.rocketchip.tilelink.LFSRNoiseMaker
 import freechips.rocketchip.util.{MaskGen, DataToAugmentedData, SeqMemToAugmentedSeqMem, PlusArg}
 

diff --git a/src/main/scala/amba/apb/Parameters.scala b/src/main/scala/amba/apb/Parameters.scala
@@ -9,8 +9,8 @@ import org.chipsalliance.cde.config.Parameters
 
 import org.chipsalliance.diplomacy.nodes.BaseNode
 
-import freechips.rocketchip.diplomacy.{AddressSet, Resource, Device, RegionType, ResourceAddress, ResourcePermissions}
-
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
+import freechips.rocketchip.resources.{Resource, Device, ResourceAddress, ResourcePermissions}
 import freechips.rocketchip.util.{BundleField, BundleKeyBase, BundleFieldBase}
 
 import scala.math.max

diff --git a/src/main/scala/amba/apb/SRAM.scala b/src/main/scala/amba/apb/SRAM.scala
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config.Parameters
 
 import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
 
-import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
+import freechips.rocketchip.resources.{DiplomaticSRAM, HasJustOneSeqMem}
 import freechips.rocketchip.tilelink.LFSRNoiseMaker
 import freechips.rocketchip.util.SeqMemToAugmentedSeqMem
 

diff --git a/src/main/scala/amba/axi4/Parameters.scala b/src/main/scala/amba/axi4/Parameters.scala
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config.Parameters
 
 import org.chipsalliance.diplomacy.nodes.BaseNode
 
-import freechips.rocketchip.diplomacy.{AddressSet, Resource, RegionType, TransferSizes, Device, ResourceAddress, ResourcePermissions, IdRange, BufferParams, IdMap, IdMapEntry, DirectedBuffers}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes, IdRange, BufferParams, IdMap, IdMapEntry, DirectedBuffers}
+import freechips.rocketchip.resources.{Resource, Device, ResourceAddress, ResourcePermissions}
 import freechips.rocketchip.util.{BundleField, BundleFieldBase, BundleKeyBase, AsyncQueueParams, CreditedDelay}
 
 import scala.math.max

diff --git a/src/main/scala/amba/axi4/SRAM.scala b/src/main/scala/amba/axi4/SRAM.scala
@@ -10,7 +10,8 @@ import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
 
 import freechips.rocketchip.amba.AMBACorrupt
-import freechips.rocketchip.diplomacy.{AddressSet, DiplomaticSRAM, HasJustOneSeqMem, RegionType, TransferSizes}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
+import freechips.rocketchip.resources.{DiplomaticSRAM, HasJustOneSeqMem}
 import freechips.rocketchip.util.{BundleMap, SeqMemToAugmentedSeqMem}
 
 /**

diff --git a/src/main/scala/amba/axis/Parameters.scala b/src/main/scala/amba/axis/Parameters.scala
@@ -7,7 +7,8 @@ import chisel3.util.{isPow2, log2Ceil}
 import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy.nodes.BaseNode
 
-import freechips.rocketchip.diplomacy.{TransferSizes, Resource, IdRange}
+import freechips.rocketchip.diplomacy.{TransferSizes, IdRange}
+import freechips.rocketchip.resources.{Resource}
 import freechips.rocketchip.util.{BundleFieldBase, BundleField}
 
 

diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala
@@ -12,7 +12,8 @@ import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.amba.apb.{APBFanout, APBToTL}
 import freechips.rocketchip.devices.debug.systembusaccess.{SBToTL, SystemBusAccessModule}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, TLBusBypass, TLError}
-import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
+import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
+import freechips.rocketchip.resources.{Description, Device, Resource, ResourceBindings, ResourceString, SimpleDevice}
 import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters, IntSyncCrossingSource, IntSyncIdentityNode}
 import freechips.rocketchip.regmapper.{RegField, RegFieldAccessType, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
 import freechips.rocketchip.rocket.{CSRs, Instructions}

diff --git a/src/main/scala/devices/tilelink/BootROM.scala b/src/main/scala/devices/tilelink/BootROM.scala
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, RegionType, Resource, SimpleDevice, TransferSizes}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
+import freechips.rocketchip.resources.{Resource, SimpleDevice}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
 

diff --git a/src/main/scala/devices/tilelink/BusBlocker.scala b/src/main/scala/devices/tilelink/BusBlocker.scala
@@ -7,7 +7,8 @@ import chisel3._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.resources.{SimpleDevice}
 import freechips.rocketchip.regmapper.{RegField, RegFieldDesc}
 import freechips.rocketchip.tilelink.{TLBusWrapper, TLFragmenter, TLNameNode, TLNode, TLRegisterNode}
 

diff --git a/src/main/scala/devices/tilelink/CLINT.scala b/src/main/scala/devices/tilelink/CLINT.scala
@@ -8,7 +8,8 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, Resource, SimpleDevice}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.resources.{Resource, SimpleDevice}
 import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
 import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
 import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}

diff --git a/src/main/scala/devices/tilelink/ClockBlocker.scala b/src/main/scala/devices/tilelink/ClockBlocker.scala
@@ -6,7 +6,8 @@ import chisel3._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.resources.{SimpleDevice}
 import freechips.rocketchip.prci.ClockAdapterNode
 import freechips.rocketchip.regmapper.{RegField, RegFieldDesc}
 import freechips.rocketchip.tilelink.TLRegisterNode

diff --git a/src/main/scala/devices/tilelink/Deadlock.scala b/src/main/scala/devices/tilelink/Deadlock.scala
@@ -5,6 +5,7 @@ package freechips.rocketchip.devices.tilelink
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.resources.{SimpleDevice}
 
 /** Adds a /dev/null slave that does not raise ready for any incoming traffic.
   * !!! WARNING: This device WILL cause your bus to deadlock for as long as you

diff --git a/src/main/scala/devices/tilelink/DevNull.scala b/src/main/scala/devices/tilelink/DevNull.scala
@@ -5,7 +5,8 @@ package freechips.rocketchip.devices.tilelink
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice, TransferSizes}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
+import freechips.rocketchip.resources.{SimpleDevice}
 import freechips.rocketchip.prci.{HasClockDomainCrossing}
 import freechips.rocketchip.tilelink.{TLManagerNode, TLSlaveParameters, TLSlavePortParameters}
 

diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.SimpleDevice
+import freechips.rocketchip.resources.SimpleDevice
 import freechips.rocketchip.tilelink.{TLArbiter, TLMessages, TLPermissions}
 
 /** Adds a /dev/null slave that generates TL error response messages */

diff --git a/src/main/scala/devices/tilelink/MaskROM.scala b/src/main/scala/devices/tilelink/MaskROM.scala
@@ -8,7 +8,8 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice, TransferSizes}
+import freechips.rocketchip.diplomacy.{RegionType, AddressSet, TransferSizes}
+import freechips.rocketchip.resources.{SimpleDevice}
 import freechips.rocketchip.subsystem.{Attachable, HierarchicalLocation, TLBusWrapperLocation}
 import freechips.rocketchip.tilelink.{TLFragmenter, TLManagerNode, TLSlaveParameters, TLSlavePortParameters, TLWidthWidget}
 import freechips.rocketchip.util.{ROMConfig, ROMGenerator}

diff --git a/src/main/scala/devices/tilelink/PhysicalFilter.scala b/src/main/scala/devices/tilelink/PhysicalFilter.scala
@@ -8,7 +8,8 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.resources.{SimpleDevice}
 import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup, RegFieldWrType, RegReadFn, RegWriteFn}
 import freechips.rocketchip.tilelink.{TLAdapterNode, TLMessages, TLPermissions, TLRegisterNode}
 

diff --git a/src/main/scala/devices/tilelink/Plic.scala b/src/main/scala/devices/tilelink/Plic.scala
@@ -9,7 +9,8 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
 import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
 import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
 import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}

diff --git a/src/main/scala/devices/tilelink/TestRAM.scala b/src/main/scala/devices/tilelink/TestRAM.scala
@@ -8,7 +8,8 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, MemoryDevice, RegionType, TransferSizes}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
+import freechips.rocketchip.resources.{MemoryDevice}
 import freechips.rocketchip.tilelink.{TLDelayer, TLFuzzer, TLManagerNode, TLMessages, TLRAMModel, TLSlaveParameters, TLSlavePortParameters}
 
 // Do not use this for synthesis! Only for simulation.

diff --git a/src/main/scala/devices/tilelink/Zero.scala b/src/main/scala/devices/tilelink/Zero.scala
@@ -8,7 +8,8 @@ import chisel3.util._
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, RegionType, SimpleDevice}
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
+import freechips.rocketchip.resources.{SimpleDevice}
 import freechips.rocketchip.tilelink.TLMessages
 
 /** This /dev/null device accepts single beat gets/puts, as well as atomics.

diff --git a/src/main/scala/diplomacy/AddressRange.scala b/src/main/scala/diplomacy/AddressRange.scala
@@ -60,21 +60,3 @@ object AddressRange
   def subtract(from: Seq[AddressRange], take: Seq[AddressRange]): Seq[AddressRange] =
     take.foldLeft(from) { case (left, r) => left.flatMap { _.subtract(r) } }
 }
-
-case class AddressMapEntry(range: AddressRange, permissions: ResourcePermissions, names: Seq[String]) {
-  val ResourcePermissions(r, w, x, c, a) = permissions
-
-  def toString(aw: Int) = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s".format(
-    range.base,
-    range.base+range.size,
-    if (a) 'A' else ' ',
-    if (r) 'R' else ' ',
-    if (w) 'W' else ' ',
-    if (x) 'X' else ' ',
-    if (c) 'C' else ' ',
-    names.mkString(", "))
-
-  def toJSON = s"""{"base":[${range.base}],"size":[${range.size}],""" +
-    s""""r":[$r],"w":[$w],"x":[$x],"c":[$c],"a":[$a],""" +
-    s""""names":[${names.map('"'+_+'"').mkString(",")}]}"""
-}
diff --git a/src/main/scala/diplomacy/package.scala b/src/main/scala/diplomacy/package.scala
@@ -21,32 +21,6 @@ package object diplomacy {
     }
   }
 
-  implicit class BigIntHexContext(private val sc: StringContext) extends AnyVal {
-    def x(args: Any*): BigInt = {
-      val orig = sc.s(args: _*)
-      BigInt(orig.replace("_", ""), 16)
-    }
-  }
-
-  type PropertyOption = Option[(String, Seq[ResourceValue])]
-  type PropertyMap = Iterable[(String, Seq[ResourceValue])]
-
-  implicit class IntToProperty(x: Int) {
-    def asProperty: Seq[ResourceValue] = Seq(ResourceInt(BigInt(x)))
-  }
-
-  implicit class BigIntToProperty(x: BigInt) {
-    def asProperty: Seq[ResourceValue] = Seq(ResourceInt(x))
-  }
-
-  implicit class StringToProperty(x: String) {
-    def asProperty: Seq[ResourceValue] = Seq(ResourceString(x))
-  }
-
-  implicit class DeviceToProperty(x: Device) {
-    def asProperty: Seq[ResourceValue] = Seq(ResourceReference(x.label))
-  }
-
   // TODO - Remove compatibility layer for deprecated diplomacy api once all local references are moved to standalone diplomacy lib.
   // package.scala
   @deprecated("Diplomacy has been split to a standalone library", "rocketchip 2.0.0")

diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala
@@ -9,7 +9,7 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{SimpleDevice}
+import freechips.rocketchip.resources.{SimpleDevice}
 import freechips.rocketchip.prci.{ClockCrossingType}
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.rocket.{BuildHellaCache, DCache, DCacheModule, ICacheParams, NonBlockingDCache, NonBlockingDCacheModule, RocketCoreParams}

diff --git a/src/main/scala/interrupts/Parameters.scala b/src/main/scala/interrupts/Parameters.scala
@@ -7,7 +7,7 @@ import chisel3.experimental.SourceInfo
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.nodes._
 
-import freechips.rocketchip.diplomacy.Resource
+import freechips.rocketchip.resources.Resource
 
 // A potentially empty half-open range; [start, end)
 case class IntRange(start: Int, end: Int)

diff --git a/src/main/scala/interrupts/RegisterRouter.scala b/src/main/scala/interrupts/RegisterRouter.scala
@@ -6,7 +6,7 @@ import chisel3._
 
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.Resource
+import freechips.rocketchip.resources.Resource
 
 import freechips.rocketchip.regmapper._
 

diff --git a/src/main/scala/prci/ClockGroup.scala b/src/main/scala/prci/ClockGroup.scala
@@ -6,7 +6,7 @@ import org.chipsalliance.diplomacy._
 import org.chipsalliance.diplomacy.lazymodule._
 import org.chipsalliance.diplomacy.nodes._
 
-import freechips.rocketchip.diplomacy.FixedClockResource
+import freechips.rocketchip.resources.FixedClockResource
 
 case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
   extends MixedNexusNode(ClockGroupImp, ClockImp)(

diff --git a/src/main/scala/prci/ClockNodes.scala b/src/main/scala/prci/ClockNodes.scala
@@ -9,7 +9,7 @@ import org.chipsalliance.diplomacy._
 import org.chipsalliance.diplomacy.lazymodule._
 import org.chipsalliance.diplomacy.nodes._
 
-import freechips.rocketchip.diplomacy.FixedClockResource
+import freechips.rocketchip.resources.FixedClockResource
 
 object ClockImp extends SimpleNodeImp[ClockSourceParameters, ClockSinkParameters, ClockEdgeParameters, ClockBundle]
 {

diff --git a/src/main/scala/regmapper/RegisterRouter.scala b/src/main/scala/regmapper/RegisterRouter.scala
@@ -9,7 +9,8 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
-import freechips.rocketchip.diplomacy.{AddressSet, Description, Device, SimpleDevice, ResourceBindings, ResourceValue}
+import freechips.rocketchip.diplomacy.{AddressSet}
+import freechips.rocketchip.resources.{Description, Device, SimpleDevice, ResourceBindings, ResourceValue}
 import freechips.rocketchip.prci.{HasClockDomainCrossing}
 
 

diff --git a/src/main/scala/resources/AddressMapEntry.scala b/src/main/scala/resources/AddressMapEntry.scala
@@ -0,0 +1,21 @@
+package freechips.rocketchip.resources
+
+import freechips.rocketchip.diplomacy.{AddressRange}
+
+case class AddressMapEntry(range: AddressRange, permissions: ResourcePermissions, names: Seq[String]) {
+  val ResourcePermissions(r, w, x, c, a) = permissions
+
+  def toString(aw: Int) = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s".format(
+    range.base,
+    range.base+range.size,
+    if (a) 'A' else ' ',
+    if (r) 'R' else ' ',
+    if (w) 'W' else ' ',
+    if (x) 'X' else ' ',
+    if (c) 'C' else ' ',
+    names.mkString(", "))
+
+  def toJSON = s"""{"base":[${range.base}],"size":[${range.size}],""" +
+    s""""r":[$r],"w":[$w],"x":[$x],"c":[$c],"a":[$a],""" +
+    s""""names":[${names.map('"'+_+'"').mkString(",")}]}"""
+}
diff --git a/src/main/scala/diplomacy/DeviceTree.scala → src/main/scala/resources/DeviceTree.scala b/src/main/scala/diplomacy/DeviceTree.scala → src/main/scala/resources/DeviceTree.scala
@@ -1,10 +1,11 @@
 // See LICENSE.SiFive for license details.
 
-package freechips.rocketchip.diplomacy
+package freechips.rocketchip.resources
 
 import org.chipsalliance.cde.config.Field
 import sys.process._
 import java.io.{ByteArrayInputStream, ByteArrayOutputStream}
+import freechips.rocketchip.diplomacy.{AddressRange}
 
 case object DTSModel    extends Field[String]
 case object DTSCompat   extends Field[Seq[String]] // -dev, -soc

diff --git a/.../scala/diplomacy/FixedClockResource.scala → .../scala/resources/FixedClockResource.scala b/.../scala/diplomacy/FixedClockResource.scala → .../scala/resources/FixedClockResource.scala
@@ -1,6 +1,6 @@
 // See LICENSE.SiFive for license details.
 
-package freechips.rocketchip.diplomacy
+package freechips.rocketchip.resources
 
 class FixedClockResource(val name: String, val freqMHz: Double, val prefix: String = "soc/")
 {

diff --git a/src/main/scala/diplomacy/JSON.scala → src/main/scala/resources/JSON.scala b/src/main/scala/diplomacy/JSON.scala → src/main/scala/resources/JSON.scala
@@ -1,8 +1,9 @@
 // See LICENSE.SiFive for license details.
 
-package freechips.rocketchip.diplomacy
+package freechips.rocketchip.resources
 
 import scala.collection.immutable.SortedMap
+import freechips.rocketchip.diplomacy.{AddressRange}
 
 object JSON
 {

diff --git a/src/main/scala/diplomacy/Resources.scala → src/main/scala/resources/Resources.scala b/src/main/scala/diplomacy/Resources.scala → src/main/scala/resources/Resources.scala
@@ -1,11 +1,13 @@
 // See LICENSE.SiFive for license details.
 
-package freechips.rocketchip.diplomacy
+package freechips.rocketchip.resources
 
 import chisel3.util.log2Ceil
 
 import scala.collection.immutable.{ListMap, SortedMap}
 import scala.collection.mutable.HashMap
+import freechips.rocketchip.diplomacy.{AddressSet, AddressRange}
+import org.chipsalliance.diplomacy.lazymodule.{LazyModule}
 
 sealed trait ResourceValue
 
@@ -275,8 +277,8 @@ trait BindingScope
   BindingScope.add(this)
 
   private val parentScope = BindingScope.find(parent)
-  protected[diplomacy] var resourceBindingFns: Seq[() => Unit] = Nil // callback functions to resolve resource binding during elaboration
-  protected[diplomacy] var resourceBindings: Seq[(Resource, Option[Device], ResourceValue)] = Nil
+  protected[resources] var resourceBindingFns: Seq[() => Unit] = Nil // callback functions to resolve resource binding during elaboration
+  protected[resources] var resourceBindings: Seq[(Resource, Option[Device], ResourceValue)] = Nil
 
   private case class ExpandedValue(path: Seq[String], labels: Seq[String], value: Seq[ResourceValue])
   private lazy val eval: Unit = {
@@ -387,8 +389,8 @@ trait BindingScope
 
 object BindingScope
 {
-  protected[diplomacy] var active: Option[BindingScope] = None
-  protected[diplomacy] def find(m: Option[LazyModule] = LazyModule.getScope): Option[BindingScope] = m.flatMap {
+  protected[resources] var active: Option[BindingScope] = None
+  protected[resources] def find(m: Option[LazyModule] = LazyModule.getScope): Option[BindingScope] = m.flatMap {
     case x: BindingScope => find(x.getParent).orElse(Some(x))
     case x => find(x.getParent)
   }