Improve NBDCache performance

src/main/scala/rocket/HellaCache.scala

@@ -119,6 +119,7 @@ trait HasCoreData extends HasCoreParameters {
 
 class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp {
   val phys = Bool()
+  val no_resp = Bool() // The dcache may omit generating a response for this request
   val no_alloc = Bool()
   val no_xcpt = Bool()
 }

src/main/scala/rocket/NBDcache.scala

@@ -68,7 +68,7 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
   val req = Reg(new HellaCacheReq)
   val grant_word = Reg(UInt(wordBits.W))
 
-  val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4)
+  val s_idle :: s_mem_access :: s_mem_ack :: s_resp_1 :: s_resp_2 :: Nil = Enum(5)
   val state = RegInit(s_idle)
   io.req.ready := (state === s_idle)
 
@@ -102,8 +102,8 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
   io.mem_access.valid := (state === s_mem_access)
   io.mem_access.bits := Mux(isAMO(req.cmd), atomics, Mux(isRead(req.cmd), get, put))
 
-  io.replay_next := (state === s_mem_ack) || io.resp.valid && !io.resp.ready
-  io.resp.valid := (state === s_resp)
+  io.replay_next := state === s_resp_1 || (state === s_resp_2 && !io.resp.ready)
+  io.resp.valid := state === s_resp_2
   io.resp.bits.addr := req.addr
   io.resp.bits.idx.foreach(_ := req.idx.get)
   io.resp.bits.tag := req.tag
@@ -130,12 +130,16 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
   }
 
   when (state === s_mem_ack && io.mem_ack.valid) {
-    state := s_resp
+    state := Mux(req.no_resp || !isRead(req.cmd), s_idle, s_resp_1)
     when (isRead(req.cmd)) {
       grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)
     }
   }
 
+  when (state === s_resp_1) {
+    state := s_resp_2
+  }
+
   when (io.resp.fire) {
     state := s_idle
   }
@@ -783,7 +787,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   when (s2_recycle) {
     s1_req := s2_req
   }
-  val s1_addr = dtlb.io.resp.paddr
+  val s1_addr = Mux(s1_req.phys, s1_req.addr, dtlb.io.resp.paddr)
 
   io.tlb_port.s1_resp := dtlb.io.resp
 
@@ -792,6 +796,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
     s2_req.signed := s1_req.signed
     s2_req.phys := s1_req.phys
     s2_req.addr := s1_addr
+    s2_req.no_resp := s1_req.no_resp
     when (s1_write) {
       s2_req.data := Mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.s1_data.data)
     }

src/main/scala/rocket/PTW.scala

@@ -534,6 +534,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
   io.mem.req.bits.dprv := PRV.S.U   // PTW accesses are S-mode by definition
   io.mem.req.bits.dv := do_both_stages && !stage2
   io.mem.req.bits.tag := DontCare
+  io.mem.req.bits.no_resp := false.B
   io.mem.req.bits.no_alloc := DontCare
   io.mem.req.bits.no_xcpt := DontCare
   io.mem.req.bits.data := DontCare

src/main/scala/rocket/RocketCore.scala

@@ -1091,6 +1091,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
   io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr)
   io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv)
   io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv
+  io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U)
   io.dmem.req.bits.no_alloc := DontCare
   io.dmem.req.bits.no_xcpt := DontCare
   io.dmem.req.bits.data := DontCare