Generalize WithNBigCores to support clustered cores

chipsalliance · Oct 17, 2023 · ef1d671 · ef1d671
1 parent f745cff
commit ef1d671
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Showing 3 changed files with 33 additions and 39 deletions.
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -90,10 +90,11 @@ class WithCoherentBusTopology extends Config((site, here, up) => {
 
 class WithNBigCores(
   n: Int,
-  crossing: RocketCrossingParams = RocketCrossingParams()
+  location: HierarchicalLocation,
+  crossing: RocketCrossingParams,
 ) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => {
-    val prev = up(TilesLocated(InSubsystem), site)
+  case TilesLocated(`location`) => {
+    val prev = up(TilesLocated(`location`), site)
     val idOffset = up(NumTiles)
     val big = RocketTileParams(
       core   = RocketCoreParams(mulDiv = Some(MulDivParams(
@@ -113,7 +114,18 @@ class WithNBigCores(
     )) ++ prev
   }
   case NumTiles => up(NumTiles) + n
-})
+}) {
+  def this(n: Int, location: HierarchicalLocation = InSubsystem) = this(n, location, RocketCrossingParams(
+    master = HierarchicalElementMasterPortParams.locationDefault(location),
+    slave = HierarchicalElementSlavePortParams.locationDefault(location),
+    mmioBaseAddressPrefixWhere = location match {
+      case InSubsystem => CBUS
+      case InCluster(clusterId) => CCBUS(clusterId)
+    }
+  ))
+}
+
+
 
 class WithNMedCores(
   n: Int,
@@ -218,38 +230,6 @@ class With1TinyCore extends Config((site, here, up) => {
   case ClustersLocated(_) => Nil
 })
 
-class WithNClusterCores(
-  n: Int,
-  clusterId: Int
-) extends Config((site, here, up) => {
-  case TilesLocated(InCluster(`clusterId`)) => {
-    val prev = up(TilesLocated(InCluster(clusterId)), site)
-    val idOffset = up(NumTiles)
-    val big = RocketTileParams(
-      core   = RocketCoreParams(mulDiv = Some(MulDivParams(
-        mulUnroll = 8,
-        mulEarlyOut = true,
-        divEarlyOut = true))),
-      dcache = Some(DCacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nMSHRs = 0,
-        blockBytes = site(CacheBlockBytes))),
-      icache = Some(ICacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        blockBytes = site(CacheBlockBytes))))
-    List.tabulate(n)(i => RocketTileAttachParams(
-      big.copy(tileId = i + idOffset),
-      RocketCrossingParams(
-        master = HierarchicalElementMasterPortParams(where=CSBUS(clusterId)),
-        slave = HierarchicalElementSlavePortParams(where=CCBUS(clusterId), blockerCtrlWhere=CCBUS(clusterId)),
-        mmioBaseAddressPrefixWhere = CCBUS(clusterId)
-      )
-    )) ++ prev
-  }
-  case NumTiles => up(NumTiles) + n
-})
-
-
 class WithCluster(
   clusterId: Int,
   location: HierarchicalLocation = InSubsystem,

diff --git a/src/main/scala/subsystem/HasHierarchicalElements.scala b/src/main/scala/subsystem/HasHierarchicalElements.scala
@@ -29,6 +29,13 @@ case class HierarchicalElementMasterPortParams(
   }
 }
 
+object HierarchicalElementMasterPortParams {
+  def locationDefault(loc: HierarchicalLocation) = loc match {
+    case InSubsystem => HierarchicalElementMasterPortParams()
+    case InCluster(clusterId) => HierarchicalElementMasterPortParams(where=CSBUS(clusterId))
+  }
+}
+
 /** A default implementation of parameterizing the connectivity of the port giving access to slaves inside the tile.
   *   Optional timing buffers and/or an optional BusBlocker adapter can be inserted in the interconnect's clock domain.
   */
@@ -51,6 +58,13 @@ case class HierarchicalElementSlavePortParams(
   }
 }
 
+object HierarchicalElementSlavePortParams {
+  def locationDefault(loc: HierarchicalLocation) = loc match {
+    case InSubsystem => HierarchicalElementSlavePortParams()
+    case InCluster(clusterId) => HierarchicalElementSlavePortParams(where=CCBUS(clusterId), blockerCtrlWhere=CCBUS(clusterId))
+  }
+}
+
 /** InstantiatesTiles adds a Config-urable sequence of HierarchicalElements of any type
   *   to the subsystem class into which it is mixed.
   */

diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
@@ -38,9 +38,9 @@ class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new Default
 class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new DefaultConfig)
 
 class ClusterConfig extends Config(
-  new WithNClusterCores(2, clusterId=3) ++
-  new WithNClusterCores(2, clusterId=1) ++
-  new WithNClusterCores(2, clusterId=0) ++
+  new WithNBigCores(2, InCluster(3)) ++
+  new WithNBigCores(2, InCluster(1)) ++
+  new WithNBigCores(2, InCluster(0)) ++
   new WithCluster(3, location=InCluster(2)) ++
   new WithCluster(2) ++
   new WithCluster(1) ++