Attach TLError LogicalTreeNodes to subsystem LogicalTreeNode

src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala

@@ -11,23 +11,36 @@ trait HasBuiltInDeviceParams {
   val errorDevice: Option[DevNullParams]
 }
 
-/* Optionally add some built-in devices to a bus wrapper */
-trait CanHaveBuiltInDevices { this: TLBusWrapper =>
+sealed trait BuiltInDevices {
+  def errorOpt: Option[TLError]
+  def zeroOpt: Option[TLZero]
+}
 
-  def attachBuiltInDevices(params: HasBuiltInDeviceParams) {
-    params.errorDevice.foreach { dnp => LazyScope("wrapped_error_device") {
+object BuiltInDevices {
+  def attach(
+    params: HasBuiltInDeviceParams with HasTLBusParams,
+    outwardNode: TLOutwardNode)(implicit p: Parameters) = new BuiltInDevices {
+    val errorOpt = params.errorDevice.map { dnp => LazyScope("wrapped_error_device") {
       val error = LazyModule(new TLError(
         params = dnp,
-        beatBytes = beatBytes))
+        beatBytes = params.beatBytes))
+
       error.node := TLBuffer() := outwardNode
+      error
     }}
 
-    params.zeroDevice.foreach { addr => LazyScope("wrapped_zero_device") {
+    val zeroOpt = params.zeroDevice.map { addr => LazyScope("wrapped_zero_device") {
       val zero = LazyModule(new TLZero(
         address = addr,
-        beatBytes = beatBytes))
-      zero.node := TLFragmenter(beatBytes, blockBytes) := TLBuffer() := outwardNode
+        beatBytes = params.beatBytes))
+      zero.node := TLFragmenter(params.beatBytes, params.blockBytes) := TLBuffer() := outwardNode
+      zero
     }}
   }
 }
 
+/* Optionally add some built-in devices to a bus wrapper */
+trait CanHaveBuiltInDevices {
+  def builtInDevices: BuiltInDevices
+}
+

src/main/scala/devices/tilelink/DevNull.scala

@@ -25,7 +25,7 @@ case class DevNullParams(
   * They may discard writes, refuse to respond to requests, issue error responses,
   * or otherwise violate 'expected' memory behavior.
   */
-abstract class DevNullDevice(params: DevNullParams, minLatency: Int, beatBytes: Int, device: SimpleDevice)
+abstract class DevNullDevice(params: DevNullParams, minLatency: Int, beatBytes: Int, protected val device: SimpleDevice)
                             (implicit p: Parameters)
     extends LazyModule with HasClockDomainCrossing {
   val xfer = if (params.maxTransfer > 0) TransferSizes(1, params.maxTransfer) else TransferSizes.none

src/main/scala/devices/tilelink/Error.scala

@@ -9,12 +9,32 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import scala.math.min
 
+import freechips.rocketchip.diplomaticobjectmodel.{DiplomaticObjectModelAddressing, HasLogicalTreeNode}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode
+import freechips.rocketchip.diplomaticobjectmodel.model.{OMErrorDevice, OMComponent}
+
 /** Adds a /dev/null slave that generates TL error response messages */
 class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters)
     extends DevNullDevice(params,
       minLatency = if (buffer) 1 else 0,
       beatBytes, new SimpleDevice("error-device", Seq("sifive,error0")))
+    with HasLogicalTreeNode
 {
+  lazy val logicalTreeNode: LogicalTreeNode = new LogicalTreeNode(() => Some(device)) {
+    def getOMComponents(resourceBindings: ResourceBindings, children: Seq[OMComponent] = Nil) = {
+      val Description(name, mapping) = device.describe(resourceBindings)
+      val memRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions(name, resourceBindings, None)
+      val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings)
+      Seq(OMErrorDevice(
+        memoryRegions = memRegions.map(_.copy(
+          name = "errordevice",
+          description = "Error Device"
+        )),
+        interrupts = interrupts
+      ))
+    }
+  }
+
   lazy val module = new LazyModuleImp(this) {
     import TLMessages._
     import TLPermissions._

src/main/scala/devices/tilelink/Zero.scala

@@ -7,6 +7,10 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink.TLMessages
 
+import freechips.rocketchip.diplomaticobjectmodel.{DiplomaticObjectModelAddressing, HasLogicalTreeNode}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode
+import freechips.rocketchip.diplomaticobjectmodel.model.{OMZeroDevice, OMComponent}
+
 /** This /dev/null device accepts single beat gets/puts, as well as atomics.
   * Response data is always 0. Reequests to write data have no effect.
   */
@@ -22,7 +26,25 @@ class TLZero(address: AddressSet, beatBytes: Int = 4)(implicit p: Parameters)
       mayDenyPut = false),
     minLatency = 1,
     beatBytes = beatBytes,
-    device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))) {
+    device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0")))
+    with HasLogicalTreeNode
+{
+
+  lazy val logicalTreeNode: LogicalTreeNode = new LogicalTreeNode(() => Some(device)) {
+    def getOMComponents(resourceBindings: ResourceBindings, children: Seq[OMComponent] = Nil) = {
+      val Description(name, mapping) = device.describe(resourceBindings)
+      val memRegions = DiplomaticObjectModelAddressing.getOMMemoryRegions(name, resourceBindings, None)
+      val interrupts = DiplomaticObjectModelAddressing.describeInterrupts(name, resourceBindings)
+      Seq(OMZeroDevice(
+        memoryRegions = memRegions.map(_.copy(
+          name = "zerodevice",
+          description = "Zero Device"
+        )),
+        interrupts = interrupts
+      ))
+    }
+  }
+
   lazy val module = new LazyModuleImp(this) {
     val (in, edge) = node.in(0)
 

src/main/scala/diplomaticobjectmodel/model/OMErrorDevice.scala

@@ -0,0 +1,10 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.diplomaticobjectmodel.model
+
+
+case class OMErrorDevice(
+  memoryRegions: Seq[OMMemoryRegion],
+  interrupts: Seq[OMInterrupt],
+  _types: Seq[String] = Seq("OMErrorDevice", "OMDevice", "OMComponent", "OMCompoundType")
+) extends OMDevice

src/main/scala/diplomaticobjectmodel/model/OMZeroDevice.scala

@@ -0,0 +1,10 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.diplomaticobjectmodel.model
+
+
+case class OMZeroDevice(
+  memoryRegions: Seq[OMMemoryRegion],
+  interrupts: Seq[OMInterrupt],
+  _types: Seq[String] = Seq("OMZeroDevice", "OMDevice", "OMComponent", "OMCompoundType")
+) extends OMDevice

src/main/scala/subsystem/BaseSubsystem.scala

@@ -81,7 +81,7 @@ case object ResetAsynchronousFull extends SubsystemResetScheme
 case object SubsystemResetSchemeKey extends Field[SubsystemResetScheme](ResetSynchronous)
 
 /** Base Subsystem class with no peripheral devices or ports added */
-abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem 
+abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem
     with Attachable {
 
   override val module: BaseSubsystemModuleImp[BaseSubsystem]
@@ -135,6 +135,24 @@ abstract class BaseSubsystem(implicit p: Parameters) extends BareSubsystem
   }
 
   lazy val logicalTreeNode = new SubsystemLogicalTreeNode()
+
+  private val buses = Seq(
+    sbus,
+    pbus,
+    fbus,
+    mbus,
+    cbus
+  )
+
+  buses.foreach { bus =>
+    val builtIn = bus.builtInDevices
+    builtIn.errorOpt.foreach { error =>
+      LogicalModuleTree.add(logicalTreeNode, error.logicalTreeNode)
+    }
+    builtIn.zeroOpt.foreach { zero =>
+      LogicalModuleTree.add(logicalTreeNode, zero.logicalTreeNode)
+    }
+  }
 }
 
 

src/main/scala/subsystem/FrontBus.scala

@@ -20,5 +20,5 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters)
     with CanHaveBuiltInDevices
     with CanAttachTLMasters
     with HasTLXbarPhy {
-  attachBuiltInDevices(params)
+  val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
 }

src/main/scala/subsystem/MemoryBus.scala

@@ -59,7 +59,7 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters)
     if (params.replicatorMask == 0) xbar.node else { xbar.node :=* RegionReplicator(params.replicatorMask) }
   def outwardNode: TLOutwardNode = ProbePicker() :*= xbar.node
   def busView: TLEdge = xbar.node.edges.in.head
-  attachBuiltInDevices(params)
+  val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
 
   def toDRAMController[D,U,E,B <: Data]
       (name: Option[String] = None, buffer: BufferParams = BufferParams.none)

src/main/scala/subsystem/PeripheryBus.scala

@@ -51,7 +51,7 @@ class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Paramet
   def outwardNode: TLOutwardNode = node
   def busView: TLEdge = fixer.node.edges.in.head
 
-  attachBuiltInDevices(params)
+  val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
 
   def toTile
       (name: Option[String] = None, buffer: BufferParams = BufferParams.none)

src/main/scala/subsystem/SystemBus.scala

@@ -29,7 +29,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters)
   def outwardNode: TLOutwardNode = system_bus_xbar.node
   def busView: TLEdge = system_bus_xbar.node.edges.in.head
 
-  attachBuiltInDevices(params)
+  val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
 
   def fromTile
       (name: Option[String], buffer: BufferParams = BufferParams.none, cork: Option[Boolean] = None)