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A Pair of Phase-Ordering Fixes #2424

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merged 2 commits into from
Apr 20, 2020
Merged

A Pair of Phase-Ordering Fixes #2424

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398a025
[stage] Mark RocketTestSuiteAnnotation as unserializable
davidbiancolin Apr 19, 2020
b9f4a5a
[stage] Have TransformAnnotations name AddImplicitOutputFile as dep
davidbiancolin Apr 19, 2020
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4 changes: 2 additions & 2 deletions src/main/scala/stage/phases/AddDefaultTests.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ import chipsalliance.rocketchip.config.Parameters
import chisel3.stage.phases.Elaborate
import firrtl.AnnotationSeq
import firrtl.annotations.NoTargetAnnotation
import firrtl.options.{Phase, PreservesAll}
import firrtl.options.{Phase, PreservesAll, Unserializable}
import firrtl.options.Viewer.view
import freechips.rocketchip.stage.RocketChipOptions
import freechips.rocketchip.subsystem.RocketTilesKey
Expand All @@ -19,7 +19,7 @@ import freechips.rocketchip.system.DefaultTestSuites._
import scala.collection.mutable

/** Annotation that contains a list of [[RocketTestSuite]]s to run */
case class RocketTestSuiteAnnotation(tests: Seq[RocketTestSuite]) extends NoTargetAnnotation
case class RocketTestSuiteAnnotation(tests: Seq[RocketTestSuite]) extends NoTargetAnnotation with Unserializable

/** Generates [[RocketTestSuiteAnnotation]] depending on whether the top-module project is part of
* [[freechips.rocketchip.system]] or not (e.g. for unit tests).
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3 changes: 1 addition & 2 deletions src/main/scala/stage/phases/TransformAnnotations.scala
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Expand Up @@ -3,7 +3,6 @@
package freechips.rocketchip.stage.phases

import chisel3.stage.ChiselOutputFileAnnotation
import chisel3.stage.phases.Emitter
import firrtl.AnnotationSeq
import firrtl.options.Viewer.view
import firrtl.options.{Phase, PreservesAll}
Expand All @@ -14,7 +13,7 @@ import freechips.rocketchip.util.HasRocketChipStageUtils
class TransformAnnotations extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {

override val prerequisites = Seq(classOf[Checks])
override val dependents = Seq(classOf[Emitter])
override val dependents = Seq(classOf[chisel3.stage.phases.AddImplicitOutputFile])

override def transform(annotations: AnnotationSeq): AnnotationSeq = {
/** Construct output file annotation for emission */
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