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Add hypervisor extension #2841

Merged
merged 52 commits into from
Dec 27, 2021
Merged

Add hypervisor extension #2841

merged 52 commits into from
Dec 27, 2021

Commits on Dec 23, 2021

  1. Add hypervisor extension 

    This PR implements v0.6.1 of the RISC-V Hypervisor Extension.

The implementation was inspired by José Martins' and colleagues' work
described in [1].  Much of the microarchitecture and essentially all of
the code is new, but their implementation served as our baseline.
We thank them for trailblazing hypervisor support in rocket-chip.

Note that this PR only includes the mechanisms to virtualize the hart
itself.  Virtualized interrupt controllers, IOMMUs, etc. are future work.
Lots of future work.

Note also that some features are (legally) not implemented.  Currently,
misa.H is not writable, something we may or may not choose to fix.
The mtval2 htval, mtinst, and htinst CSRs are hardwired to 0, placing
additional onus on hypervisor software.  We think it's likely we'll
eventually implement these CSRs less trivially, at least in some cases.

[1] "A First Look at RISC-V Virtualization from an Embedded Systems Perspective", https://arxiv.org/abs/2103.14951
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  2. maintain same width of MIP CSR bit positions 'lip'

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  3. CSR Decode: Expanded Instruction for c.ebreak

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  4. drop 'd' from TLBReq.dprv/dv also driven by instruction request

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  5. Object Model: useHypervisor param

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  6. PTW: pad request address in s1_ppns

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  7. guest XLen fixed static value

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  8. GEILEN=0, so tie off HStatus.VGEIN

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  9. GEILEN=0, so tie off HGEIE/HGEIP

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  10. GEILEN=0, so mask off SGEIP

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  11. untie vsstatus.SXL [bit 35]

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  12. mstatus.GVA should be set by load/store fault with DV=1

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  13. allow HSV in U-mode when hstatus.HU=1

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  14. Stage-1 PTW DV from VS-mode

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  15. PTW: consider full GPA when indexing PTE cache

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  16. PTW: support GPAs larger than VA size

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  17. TLB: support GPAs larger than VA size

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  18. PTW: use correct indexing function for PTE cache

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  19. Raise correct exception when VU-mode counter access is disabled

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  20. stage2 pte cache data entry width

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  21. flush guest TLB entries on guest Bare <-> SvXX transitions

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  22. ISA: Neither mstatus.TVM nor hstatus.VTVM causes HFENCE.VVMA to trap.

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  23. Update the aux_count value to be 0 when vstage1 is disabled. RTL inco… 

    …rrectly taking store access fault when stage1 MMU off.
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  24. DTS: add Hypervisor hgatp modes to mmu-type

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  25. width of hcounteren should be controlled by nPerfCounters

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  26. satp/vsatp/hgatp.MODE should reset to legal value (off)

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  27. TLB/PTW: add htval/mtval2 support

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  28. CSRFile: add htval/mtval2 support

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  29. D$: add htval/mtval2 support

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  30. I$: add htval/mtval2 support

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  31. rocket: add htval/mtval2 support 

    The change to take_pc_mem is necessary to guarantee that the GPA from
the frontend is still valid at commit.
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  32. RoccBlackBox: add input rocc_mem_s2_gpa

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  33. TLB vstage1_en usingHypervisor

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  34. PTW set stage2_final when !vstage1

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  35. don't populate htval for regular page fault or misaligned

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  36. TLB: optimize uses of (v)stage1_en

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  37. invalidate fragmented TLB entry on hfence.vvma

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  38. CSRFileIO.htval same width as reg_htval/mtval2

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  39. PTW: optimize more uses of vsatp instead of muxed satp

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  40. L1TLB: pass-through requests should hit

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  41. RNMI: Add MPV field to capture virtualization mode upon NMI

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  42. do not take virtual instruction fault on write access to read-only CSR

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  43. TLB: fix GPA-acquisition livelock

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  44. CSR: vstvec/stvec width = vaddrBitsExtended

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  45. TLB: correctly propagate LSBs of GPA

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  46. L2TLB allocation should ignore G-stage PTE Global bit

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  47. read_mideleg do not OR-on local interrupts always from hs_delegable_i… 

    …nterrupts
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  48. L1TLB timing: superpage GPA miss invalidate

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  49. PTW coverage: PTE cache hit level cover stage2 use aux_count

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  50. TLB GPA need not come back as a fragmented superpage entry

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  51. PTW: Stage-2 should check for a PPN-out-of-range access fault before … 

    …continuing to Stage-1
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  52. VS-disabled mtval2/htval should correspond exactly to mtval/stval>>2

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