Sync master with dev

.github/workflows/mill-ci.yml

@@ -11,9 +11,11 @@ env:
 on:
   push:
     branches:
+      - dev
       - master
   pull_request:
     branches:
+      - dev
       - master
       - chisel3_port
 
@@ -39,14 +41,14 @@ jobs:
 
       - name: run riscv-tests
         run: |
-          nix --experimental-features 'nix-command flakes' develop -c mill -i -j 0 "runnable-test[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.${{ matrix.config }},_,_].run"
+          nix --experimental-features 'nix-command flakes' develop -c mill -i -j 0 "runnable-riscv-test[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.${{ matrix.config }},_,_].run"
 
   emulator:
     name: emulator
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        config: [DefaultSmallConfig, DualBankConfig, DualChannelConfig, DualChannelDualBankConfig, RoccExampleConfig, Edge128BitConfig, Edge32BitConfig, QuadChannelBenchmarkConfig, EightChannelConfig, DualCoreConfig, MemPortOnlyConfig, MMIOPortOnlyConfig, CloneTileConfig]
+        config: [DefaultSmallConfig, DualBankConfig, DualChannelConfig, DualChannelDualBankConfig, RoccExampleConfig, Edge128BitConfig, Edge32BitConfig, QuadChannelBenchmarkConfig, EightChannelConfig, DualCoreConfig, MemPortOnlyConfig, MMIOPortOnlyConfig, CloneTileConfig, HypervisorConfig]
     steps:
       - uses: actions/checkout@v2
         with:
@@ -67,6 +69,7 @@ jobs:
   riscv-arch-test:
     name: riscv-arch-test
     runs-on: [self-hosted, linux]
+    if: ${{ false }}  # disable for now, I prefer adding firesim-based simulation framework in the future.
     strategy:
       matrix:
         config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei", "BitManipCryptoConfig,64,RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh", "BitManipCrypto32Config,32,RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"]
@@ -87,3 +90,27 @@ jobs:
       - name: run riscv-arch-test
         run: |
           nix develop -c mill -i -j 0 "runnable-arch-test[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.${{ matrix.config }}].run"
+
+  jtag-dtm-test:
+    name: jtag-dtm-test
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        config: ["freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultConfig", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultRV32Config", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultConfig", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultRV32Config"]
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: 'true'
+
+      - name: install nix
+        uses: cachix/install-nix-action@v19
+        with:
+          install_url: https://releases.nixos.org/nix/nix-2.13.3/install
+          nix_path: nixpkgs=channel:nixos-unstable
+
+      - name: Coursier Cache
+        uses: coursier/cache-action@v6
+
+      - name: run jtag-dtm-test
+        run: |
+          nix develop -c mill -i -j 0 "runnable-jtag-dtm-test[freechips.rocketchip.system.TestHarness,${{ matrix.config }},_,_,_].run"

.mergify.yml

@@ -0,0 +1,13 @@
+pull_request_rules:
+- name: backport to master
+  conditions:
+  - merged
+  - base=dev
+  - label=backport
+  actions:
+    backport:
+      branches:
+      - master
+      labels:
+      - backporting
+      ignore_conflicts: true

CONTRIBUTING.md

@@ -77,6 +77,6 @@ Please see the Github documentation for [Pull Requests](https://help.github.com/
 
 Because Chisel and FIRRTL have mature release processes, Rocket Chip uses the published artifacts.
 
-To bump the published dependencies, bump the versions at the top of the SBT build file: [build.sbt](build.sbt).
+To bump the published dependencies, bump the versions at the top of the Mill build file: [build.sc](build.sc).
 Typically, the SBT dependency will only list a version for Chisel 3 which itself depends on FIRRTL.
 

Makefrag

@@ -25,7 +25,7 @@ EMPTY :=
 SPACE := $(EMPTY) $(EMPTY)
 COMMA := ,
 
-SBT ?= java -Xmx$(JVM_MEMORY) -Xss8M -jar $(base_dir)/sbt-launch.jar
+MILL ?= mill
 SHELL := /bin/bash
 
 FIRRTL_TRANSFORMS := \
@@ -37,16 +37,14 @@ JAVA ?= java -Xmx$(JVM_MEMORY) -Xss8M
 FIRRTL ?= $(JAVA) -cp $(ROCKET_CHIP_JAR) firrtl.stage.FirrtlMain
 GENERATOR ?= $(JAVA) -cp $(ROCKET_CHIP_JAR) $(PROJECT).Generator
 
-# Extracting this information from SBT would be more robust
-# api-config-chipsalliance does not use standard SBT src/main/scala, but has no resources
-scala_srcs := $(shell find $(base_dir) -name "*.scala" -o -name "*.sbt")
+scala_srcs := $(shell find $(base_dir) -name "*.scala" -o -name "*.sc")
 resource_dirs := $(shell find $(base_dir) -type d -path "*/src/main/resources")
 resources := $(foreach d,$(resource_dirs),$(shell find $(d) -type f))
 all_srcs := $(scala_srcs) $(resources)
 
-ROCKET_CHIP_JAR := $(base_dir)/rocketchip.jar
+ROCKET_CHIP_JAR := $(base_dir)/out/rocketchip/assembly.dest/out.jar
 $(ROCKET_CHIP_JAR): $(all_srcs)
-	cd $(base_dir) && $(SBT) assembly
+	cd $(base_dir) && $(MILL) rocketchip.assembly
 
 rc_resource_dir := $(base_dir)/src/main/resources
 csrc := $(rc_resource_dir)/csrc

README.md

@@ -94,20 +94,6 @@ To generate FPGA- or VLSI-synthesizable Verilog (output will be in `vsim/generat
     $ cd vsim
     $ make verilog
 
-To run the Scala tests (`sbt test`) or linter (`sbt scalafix`):
-
-    $ cd regression
-
-    # Scala tests
-    $ make scalatest SUITE=foo
-
-    # Scala linter, automatically modifying files to correct issues
-    $ make scalafix SUITE=foo
-
-    # Scala linter, only printing out issues
-    $ make scalafix-check SUITE=foo
-
-
 ### Keeping Your Repo Up-to-Date
 
 If you are trying to keep your repo up to date with this GitHub repo,
@@ -229,8 +215,6 @@ C sources for use with Verilator simulation.
 Documentation, tutorials, etc for specific parts of the codebase.
 * **emulator**
 Directory in which Verilator simulations are compiled and run.
-* **project**
-Directory used by SBT for Scala compilation and build.
 * **regression**
 Defines continuous integration and nightly regression suites.
 * **scripts**
@@ -694,12 +678,46 @@ Now we can proceed as with Spike, debugging works in a similar way:
 
 Further information about GDB debugging is available [here](https://sourceware.org/gdb/onlinedocs/gdb/) and [here](https://sourceware.org/gdb/onlinedocs/gdb/Remote-Debugging.html#Remote-Debugging).
 
-## <a name="ide"></a> Building Rocket Chip with an IDE
+## <a name="ide"></a> IDEs Support
+
+The Rocket Chip Scala build uses [mill](https://github.com/com-lihaoyi/mill) as build tool.
+
+IDEs like [IntelliJ](https://www.jetbrains.com/idea/) and [VSCode](https://code.visualstudio.com/) are popular in the Scala community and work with Rocket Chip.
+
+The Rocket Chip currently uses `nix` to configure the build and/or development environment, you need to install it first depending on your OS distro.
+
+Then follow the steps:
+
+1. Generate BSP config by running:
+
+   ```
+   mill mill.bsp.BSP/install
+   ```
+
+2. Patch the `argv` in `.bsp/mill-bsp.json`, from
+
+   ```json
+   {"name":"mill-bsp","argv":["/usr/bin/mill","--bsp","--disable-ticker","--color","false","--jobs","1"],"millVersion":"0.10.9","bspVersion":"2.0.0","languages":["scala","java"]}
+   ```
+
+   to
+
+   ```json
+   {"name":"mill-bsp","argv":["/usr/bin/nix","develop","-c","mill","--bsp","--disable-ticker","--color","false","--jobs","1"],"millVersion":"0.10.9","bspVersion":"2.0.0","languages":["scala","java"]}
+   ```
+
+### For IntelliJ users
+
+3. Install and configure [Scala](https://plugins.jetbrains.com/plugin/1347-scala) plugin.
+
+4. BSP should be automatically run.
+   If it doesn't, click `bsp` on the right bar, then right-click on your project to reload.
+
+### For VSCode users
+
+3. Install and configure [Metals](https://marketplace.visualstudio.com/items?itemName=scalameta.metals) extension.
 
-The Rocket Chip Scala build uses the standard Scala build tool SBT.
-IDEs like [IntelliJ](https://www.jetbrains.com/idea/) and [VSCode](https://code.visualstudio.com/)
-are popular in the Scala community and work with Rocket Chip.
-To use one of these IDEs, there is one minor peculiarity of the Rocket Chip build that must be addressed.
+4. Execute VSCode command `Metals: Import build`.
 
 ## <a name="contributors"></a> Contributors