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Merge pull request #31 from chipsalliance/dependabot/submodules/riscv…
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…-isa-sim-3349dc5

Bump riscv-isa-sim from `adfaef0` to `3349dc5`
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@sequencer
sequencer authored Dec 22, 2022
2 parents 9536c88 + 603905f commit 04a559f
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion riscv-isa-sim
Submodule riscv-isa-sim updated from adfaef to 3349dc

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