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Make compile for Yosys 0.37 #2300

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Make compile for Yosys 0.37 #2300

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25 changes: 23 additions & 2 deletions frontends/systemverilog/uhdm_common_frontend.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -151,8 +151,29 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve
AST::AstNode *current_ast = parse(filename);

if (current_ast) {
AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, false, false, false, false, false,
false, false, false, false, false, dont_redefine, false, defer, default_nettype_wire);
AST::process(design, current_ast,
false, // nodisplay (came with Yosys 0.37)
dump_ast1, //
dump_ast2, //
no_dump_ptr, //
dump_vlog1, //
dump_vlog2, //
dump_rtlil, //
false, // nolatches
false, // nomeminit
false, // nomem2reg
false, // mem2reg
false, // noblackbox
false, // lib
false, // nowb
false, // noopt
false, // icells
false, // pwires
dont_redefine, // nooverwrite
false, // overwrite
defer, // defer
default_nettype_wire // autowire
);
delete current_ast;
}
}
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2 changes: 1 addition & 1 deletion third_party/yosys
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Submodule yosys updated 40 files
+4 −1 .github/workflows/test-linux.yml
+5 −2 .github/workflows/test-macos.yml
+16 −2 CHANGELOG
+2 −2 Makefile
+112 −51 backends/cxxrtl/cxxrtl_backend.cc
+209 −111 backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+783 −0 backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
+231 −0 backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h
+103 −37 backends/verilog/verilog_backend.cc
+3 −1 docs/source/CHAPTER_CellLib.rst
+22 −2 frontends/ast/ast.cc
+6 −3 frontends/ast/ast.h
+1 −1 frontends/ast/genrtlil.cc
+208 −151 frontends/ast/simplify.cc
+1 −1 frontends/verific/verific.cc
+10 −1 frontends/verilog/verilog_frontend.cc
+59 −81 kernel/fmt.cc
+6 −5 kernel/fmt.h
+10 −2 kernel/hashlib.h
+1 −1 passes/cmds/show.cc
+1 −1 passes/cmds/stat.cc
+30 −0 passes/hierarchy/hierarchy.cc
+3 −3 passes/memory/memory_libmap.cc
+27 −29 passes/opt/opt_lut.cc
+2 −1 passes/sat/recover_names.cc
+37 −1 passes/sat/sim.cc
+28 −24 techlibs/gowin/brams_map.v
+1 −1 techlibs/ice40/synth_ice40.cc
+3 −3 techlibs/quicklogic/ql_bram_merge.cc
+5 −4 techlibs/quicklogic/ql_dsp_io_regs.cc
+35 −35 techlibs/quicklogic/ql_dsp_simd.cc
+6 −1 tests/fmt/always_full_tb.cc
+20 −0 tests/simple/sign_part_assign.v
+3 −3 tests/svtypes/typedef_scopes.sv
+18 −0 tests/various/dynamic_part_select.ys
+20 −0 tests/various/dynamic_part_select/forloop_select_nowrshmsk.v
+10 −0 tests/verific/clocking.ys
+1 −1 tests/verilog/dynamic_range_lhs.sh
+5 −5 tests/verilog/dynamic_range_lhs.v
+65 −0 tests/verilog/roundtrip_proc.ys
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