[rtl] use scanRightOr in chisel3 utils

chipsalliance · Feb 16, 2023 · db272d1 · db272d1
1 parent 5c0a59c
commit db272d1
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Showing 2 changed files with 2 additions and 37 deletions.
diff --git a/tilelink/src/utils/package.scala b/tilelink/src/utils/package.scala
diff --git a/tilelink/src/xbar/TLArbiter.scala b/tilelink/src/xbar/TLArbiter.scala
@@ -47,8 +47,8 @@ class TLArbiter(val parameter: TLArbiterParameter)
             val valid   = valids(width - 1, 0)
             assert(valid === valids)
             val mask    = RegInit(((BigInt(1) << width) - 1).U(width - 1, 0))
-            val filter  = Cat(valid & (~mask).asUInt, valid)
-            val unready = (rightOR(filter, width * 2, width) >> 1).asUInt | (mask << width).asUInt
+            val filter  = Cat(scanRightOr(valid & ~mask), valid)
+            val unready = (filter >> 1).asUInt | (mask << width).asUInt
             val readys  = (~((unready >> width).asUInt & unready(width - 1, 0))).asUInt
             when(select && valid.orR) {
               mask := scanLeftOr(readys & valid)