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Invalid namespace reference in generated VHDL (for Synplify) #1996

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basile-henry opened this issue Nov 11, 2021 · 3 comments · Fixed by #1997
Closed

Invalid namespace reference in generated VHDL (for Synplify) #1996

basile-henry opened this issue Nov 11, 2021 · 3 comments · Fixed by #1997
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@basile-henry
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basile-henry commented Nov 11, 2021

Clash generates VHDL that is not considered valid by Synopsis' Synplify Pro tool.

The following clash code:

import Clash.Prelude

topEntity :: (Int, Int) -> (Int, Int)
topEntity = id

Generates the following VHDL for the types file (the topentity.vhdl is straight forward and not relevant for this issue):

vhdl/Main/main_types.vhdl:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

package main_types is

  type tup2 is record
    tup2_sel0_signed_0 : signed(63 downto 0);
    tup2_sel1_signed_1 : signed(63 downto 0);
  end record;
  function toSLV (s : in signed) return std_logic_vector;
  function fromSLV (slv : in std_logic_vector) return signed;
  function toSLV (p : main_types.tup2) return std_logic_vector;
  function fromSLV (slv : in std_logic_vector) return main_types.tup2;
end;

package body main_types is
  function toSLV (s : in signed) return std_logic_vector is
  begin
    return std_logic_vector(s);
  end;
  function fromSLV (slv : in std_logic_vector) return signed is
    alias islv : std_logic_vector(0 to slv'length - 1) is slv;
  begin
    return signed(islv);
  end;
  function toSLV (p : main_types.tup2) return std_logic_vector is
  begin
    return (toSLV(p.tup2_sel0_signed_0) & toSLV(p.tup2_sel1_signed_1));
  end;
  function fromSLV (slv : in std_logic_vector) return main_types.tup2 is
  alias islv : std_logic_vector(0 to slv'length - 1) is slv;
  begin
    return (fromSLV(islv(0 to 63)),fromSLV(islv(64 to 127)));
  end;
end;

Synplify Pro errors out with:

error[CD157]: Expecting return type name
  --> /nix/store/94wz1fddc9swincshkykr1rric41dwsm-virtual-simple-src/rtl/vhdl/Main/main_types.vhdl:14:54
   |
14 |   function fromSLV (slv : in std_logic_vector) return main_types.tup2;
   |                                                       ^^^^^^^^^^

error[CD157]: Expecting return type name
  --> /nix/store/94wz1fddc9swincshkykr1rric41dwsm-virtual-simple-src/rtl/vhdl/Main/main_types.vhdl:31:54
   |
31 |   function fromSLV (slv : in std_logic_vector) return main_types.tup2 is
   |                                                       ^^^^^^^^^^

The issue as far as I understand it is that Synplify Pro doesn't like qualified/namespaced names used inside of the namespace definition itself. Maybe it's not in scope yet?
It could very well just be an issue with that tool, since Vivado and Quartus are happy with such VHDL. But it would be nice for Clash to generate code without these qualified names. Do these even need to be qualified anyway? Is it ever ambiguous what they refer to? If so, maybe Clash could have a flag to opt in to generate unqualified names.
The current workaround we have is to apply sed -i '/^use work/b; s/main_types\.//g' to this type file, after which Synplify Pro works just fine.

@basile-henry
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basile-henry commented Nov 11, 2021

I should have specified, this is Clash 1.2, I have not tested on a more recent version yet.

alex-mckenna pushed a commit that referenced this issue Nov 11, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.
alex-mckenna pushed a commit that referenced this issue Nov 11, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.
alex-mckenna pushed a commit that referenced this issue Nov 11, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.
alex-mckenna pushed a commit that referenced this issue Nov 11, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.
mergify bot pushed a commit that referenced this issue Nov 11, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

(cherry picked from commit 5c6bf8b)

# Conflicts:
#	clash-lib/src/Clash/Backend/VHDL.hs
alex-mckenna pushed a commit that referenced this issue Nov 12, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

(cherry picked from commit 5c6bf8b)
alex-mckenna pushed a commit that referenced this issue Nov 12, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

(cherry picked from commit 5c6bf8b)
alex-mckenna pushed a commit that referenced this issue Nov 12, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

(cherry picked from commit 5c6bf8b)
mergify bot pushed a commit that referenced this issue Nov 12, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

(cherry picked from commit 5c6bf8b)

# Conflicts:
#	clash-lib/src/Clash/Backend/VHDL.hs
#	tests/Main.hs
alex-mckenna pushed a commit that referenced this issue Nov 12, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

(cherry picked from commit 5c6bf8b)
alex-mckenna pushed a commit that referenced this issue Nov 12, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

NOTE: To avoid backporting the changes for compatibility with
prettyprinter-1.7.1, a more restrictive bound is set in this branch.

(cherry picked from commit 5c6bf8b)
alex-mckenna pushed a commit that referenced this issue Nov 12, 2021
Similar to ece7f26 for SystemVerilog, types should not appear
qualified in the package body for the types package in VHDL.

Fixes #1996.

NOTE: To avoid backporting the changes for compatibility with
prettyprinter-1.7.1, a more restrictive bound is set in this branch.

(cherry picked from commit 5c6bf8b)
@alex-mckenna
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@basile-henry The fix for this has been backported to 1.4 and 1.2 now. I don't think we automate builds from the 1.2 branch anymore though, but it gives you a way to get the fix without forcing you to upgrade to 1.4 immediately

@basile-henry
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basile-henry commented Nov 15, 2021

Great, thank you very much @alex-mckenna ! I can confirm this fix on the 1.2 branch fixes our issue. 🎉 😄

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