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Changed monitor sample to prepone region of correct clock edge #28

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merged 1 commit into from
Oct 20, 2021
Merged

Changed monitor sample to prepone region of correct clock edge #28

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6 changes: 1 addition & 5 deletions src/cocotb_bus/monitors/avalon.py
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
import warnings

from cocotb.utils import hexdump
from cocotb.triggers import RisingEdge, ReadOnly
from cocotb.triggers import RisingEdge
from cocotb.binary import BinaryValue

from cocotb_bus.monitors import BusMonitor
Expand Down Expand Up @@ -49,7 +49,6 @@ async def _monitor_recv(self):

# Avoid spurious object creation by recycling
clkedge = RisingEdge(self.clock)
rdonly = ReadOnly()

def valid():
if hasattr(self.bus, "ready"):
Expand All @@ -59,7 +58,6 @@ def valid():
# NB could await on valid here more efficiently?
while True:
await clkedge
await rdonly
if valid():
vec = self.bus.data.value
vec.big_endian = self.config["firstSymbolInHighOrderBits"]
Expand Down Expand Up @@ -130,7 +128,6 @@ async def _monitor_recv(self):

# Avoid spurious object creation by recycling
clkedge = RisingEdge(self.clock)
rdonly = ReadOnly()
pkt = b""
in_pkt = False
invalid_cyclecount = 0
Expand All @@ -143,7 +140,6 @@ def valid():

while True:
await clkedge
await rdonly

if self.in_reset:
continue
Expand Down