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update to embedded-hal:1.0.0-alpha.10 #66

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Apr 15, 2023
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4 changes: 2 additions & 2 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -20,5 +20,5 @@ include = [
edition = "2018"

[dependencies]
embedded-hal = "=1.0.0-alpha.9"
embedded-hal-nb = "=1.0.0-alpha.1"
embedded-hal = "=1.0.0-alpha.10"
embedded-hal-nb = "=1.0.0-alpha.2"
12 changes: 3 additions & 9 deletions src/delay.rs
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,6 @@
//! [`std::thread::sleep`](https://doc.rust-lang.org/std/thread/fn.sleep.html)
//! to implement the delay.

use core::convert::Infallible;
use std::thread;
use std::time::Duration;

Expand All @@ -35,11 +34,9 @@ impl Default for MockNoop {
}

impl delay::DelayUs for MockNoop {
type Error = Infallible;

/// A no-op delay implementation.
fn delay_us(&mut self, _n: u32) -> Result<(), Self::Error> {
Ok(())
fn delay_us(&mut self, _n: u32) {
// no-op
}
}

Expand All @@ -60,11 +57,8 @@ impl Default for StdSleep {
}

impl delay::DelayUs for StdSleep {
type Error = Infallible;

/// A `Delay` implementation that uses `std::thread::sleep`.
fn delay_us(&mut self, n: u32) -> Result<(), Self::Error> {
fn delay_us(&mut self, n: u32) {
thread::sleep(Duration::from_micros(n as u64));
Ok(())
}
}
7 changes: 7 additions & 0 deletions src/error.rs
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
use std::{error::Error as StdError, fmt, io};
use embedded_hal::digital::ErrorKind::{self, Other};

/// Errors that may occur during mocking.
#[derive(PartialEq, Clone, Debug)]
Expand All @@ -7,6 +8,12 @@ pub enum MockError {
Io(io::ErrorKind),
}

impl embedded_hal::digital::Error for MockError {
fn kind(&self) -> ErrorKind {
Other
}
}

impl From<io::Error> for MockError {
fn from(e: io::Error) -> Self {
MockError::Io(e.kind())
Expand Down
151 changes: 0 additions & 151 deletions src/i2c.rs
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,6 @@
//!
//! - `Read`: This expects an I²C `read` command and will return the wrapped bytes.
//! - `Write`: This expects an I²C `write` command with the wrapped bytes.
//! - `WriteRead`: This expects an I²C `write_read` command where the
//! `expected` bytes are written and the `response` bytes are returned.
//!
//! ## Testing Error Handling
Expand Down Expand Up @@ -227,31 +226,6 @@ impl i2c::I2c for Mock {
}
}

fn write_iter<B>(&mut self, address: u8, bytes: B) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
let w = self
.next()
.expect("no pending expectation for i2c::write call");

assert_eq!(
w.expected_mode,
Mode::Write,
"i2c::write_iter unexpected mode"
);
assert_eq!(w.expected_addr, address, "i2c::write_iter address mismatch");
assert!(
bytes.into_iter().eq(w.expected_data),
"i2c::write_iter data does not match expectation"
);

match w.expected_err {
Some(err) => Err(err),
None => Ok(()),
}
}

fn write_read(
&mut self,
address: u8,
Expand Down Expand Up @@ -288,48 +262,6 @@ impl i2c::I2c for Mock {
}
}

fn write_iter_read<B>(
&mut self,
address: u8,
bytes: B,
buffer: &mut [u8],
) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
let w = self
.next()
.expect("no pending expectation for i2c::write_read call");

assert_eq!(
w.expected_mode,
Mode::WriteRead,
"i2c::write_iter_read unexpected mode"
);
assert_eq!(
w.expected_addr, address,
"i2c::write_iter_read address mismatch"
);
assert!(
bytes.into_iter().eq(w.expected_data),
"i2c::write_iter_read write data does not match expectation"
);

assert_eq!(
buffer.len(),
w.response_data.len(),
"i2c::write_iter_read mismatched response length"
);

match w.expected_err {
Some(err) => Err(err),
None => {
buffer.copy_from_slice(&w.response_data);
Ok(())
}
}
}

fn transaction<'a>(
&mut self,
address: u8,
Expand Down Expand Up @@ -365,41 +297,6 @@ impl i2c::I2c for Mock {

Ok(())
}

fn transaction_iter<'a, O>(&mut self, address: u8, operations: O) -> Result<(), Self::Error>
where
O: IntoIterator<Item = i2c::Operation<'a>>,
{
let w = self
.next()
.expect("no pending expectation for i2c::transaction call");

assert_eq!(
w.expected_mode,
Mode::TransactionStart,
"i2c::transaction_start unexpected mode"
);

for op in operations {
match op {
i2c::Operation::Read(r) => self.read(address, r),
i2c::Operation::Write(w) => self.write(address, w),
}
.unwrap();
}

let w = self
.next()
.expect("no pending expectation for i2c::transaction call");

assert_eq!(
w.expected_mode,
Mode::TransactionEnd,
"i2c::transaction_end unexpected mode"
);

Ok(())
}
}

#[cfg(test)]
Expand All @@ -418,16 +315,6 @@ mod test {
i2c.done();
}

#[test]
fn test_i2c_mock_write_iter() {
let expectations = [Transaction::write(0xaa, vec![10, 12])];
let mut i2c = Mock::new(&expectations);

i2c.write_iter(0xaa, vec![10, 12]).unwrap();

i2c.done();
}

#[test]
fn test_i2c_mock_read() {
let expectations = [Transaction::read(0xaa, vec![1, 2])];
Expand All @@ -453,19 +340,6 @@ mod test {
i2c.done();
}

#[test]
fn test_i2c_mock_write_iter_read() {
let expectations = [Transaction::write_read(0xaa, vec![1, 2], vec![3, 4])];
let mut i2c = Mock::new(&expectations);

let v = vec![1, 2];
let mut buff = vec![0u8; 2];
i2c.write_iter_read(0xaa, v, &mut buff).unwrap();
assert_eq!(vec![3, 4], buff);

i2c.done();
}

#[test]
fn test_i2c_mock_multiple() {
let expectations = [
Expand Down Expand Up @@ -509,31 +383,6 @@ mod test {
i2c.done();
}

#[test]
fn test_i2c_mock_multiple_transaction_iter() {
let expectations = [
Transaction::transaction_start(0xaa),
Transaction::write(0xaa, vec![1, 2]),
Transaction::read(0xaa, vec![3, 4]),
Transaction::transaction_end(0xaa),
];
let mut i2c = Mock::new(&expectations);

let mut v = vec![0u8; 2];
i2c.transaction_iter(
0xaa,
[
i2c::Operation::Write(&vec![1, 2]),
i2c::Operation::Read(&mut v),
],
)
.unwrap();

assert_eq!(v, vec![3, 4]);

i2c.done();
}

#[test]
#[should_panic]
fn test_i2c_mock_write_err() {
Expand Down
59 changes: 44 additions & 15 deletions src/spi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@
//! spi.done();
//! ```
use embedded_hal::spi;
use embedded_hal::spi::ErrorKind;
use embedded_hal::spi::{ErrorKind, Operation, SpiBusRead, SpiBusWrite, SpiDeviceRead, SpiDeviceWrite};
use embedded_hal::spi::ErrorType;
use embedded_hal::spi::SpiBusFlush;
use embedded_hal_nb::nb;
Expand Down Expand Up @@ -297,16 +297,31 @@ impl FullDuplex<u8> for Mock {
}
}

impl spi::SpiDevice for Mock {
type Bus = Mock;
impl SpiDeviceRead<u8> for Mock {
fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
for op in operations {
SpiBusRead::read(self, op)?;
}

Ok(())
}
}

impl SpiDeviceWrite<u8> for Mock {
fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
for op in operations {
SpiBusWrite::write(self, op)?;
}

Ok(())
}
}

impl spi::SpiDevice for Mock {
/// spi::SpiDevice implementation for Mock
///
/// This writes the provided response to the buffer and will cause an assertion if the written data does not match the next expectation
fn transaction<R>(
&mut self,
f: impl FnOnce(&mut Self::Bus) -> Result<R, <Self::Bus as ErrorType>::Error>,
) -> Result<R, Self::Error> {
fn transaction(&mut self, operations: &mut [Operation<'_, u8>]) -> Result<(), Self::Error> {
let w = self
.next()
.expect("no expectation for spi::transaction call");
Expand All @@ -316,7 +331,22 @@ impl spi::SpiDevice for Mock {
"spi::transaction unexpected mode"
);

let result = f(self);
for op in operations {
match op {
Operation::Read(buffer) => {
SpiBusRead::read(self, buffer)?;
}
Operation::Write(buffer) => {
SpiBusWrite::write(self, buffer)?;
}
Operation::Transfer(read, write) => {
spi::SpiBus::transfer(self, read, write)?;
}
Operation::TransferInPlace(buffer) => {
spi::SpiBus::transfer_in_place(self, buffer)?;
}
}
}

let w = self
.next()
Expand All @@ -327,7 +357,7 @@ impl spi::SpiDevice for Mock {
"spi::transaction unexpected mode"
);

result
Ok(())
}
}

Expand Down Expand Up @@ -413,12 +443,11 @@ mod test {
];
let mut spi = Mock::new(&expectations);
let mut ans = [0u8; 1];
spi.transaction(|mut spi| {
SpiBusWrite::write(&mut spi, &[1, 2]).unwrap();
SpiBusWrite::write(&mut spi, &[0x09]).unwrap();
SpiBusRead::read(&mut spi, &mut ans)
})
.unwrap();
spi.transaction(&mut [
Operation::Write(&[1,2]),
Operation::Write(&[0x09]),
Operation::Read(&mut ans),
]).unwrap();

assert_eq!(ans, [10]);

Expand Down