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1. Hardware-Accelerated-Transformer-Attention Hardware-Accelerated-Transformer-Attention Public

   A SystemVerilog implementation of the Scaled Dot-Product Attention mechanism for transformer neural networks, featuring pipelined matrix multiplication and SRAM-based memory architecture.

   Verilog 5

2. RISC-V-Core-with-Integrated-CNN-Accelerator RISC-V-Core-with-Integrated-CNN-Accelerator Public

   A high-performance 32-bit RISC-V processor core with an integrated CNN accelerator, implemented on Xilinx Nexys A7 FPGA. This project combines general-purpose computing capabilities with specialize…

   Verilog 5

3. Branch-Predictor-Simulator Branch-Predictor-Simulator Public

   This project implements a configurable branch predictor simulator that supports different types of branch prediction schemes. The simulator reads branch traces and evaluates the prediction accuracy…

   C++

4. Multilevel-Cache-Simulator-with-Prefetch Multilevel-Cache-Simulator-with-Prefetch Public

   A C++ simulator for L1/L2 cache levels with a configurable stream-buffer prefetch unit, implementing the WBWA policy.

   C++

5. Out-of-Order-Superscalar-Processor-Simulator Out-of-Order-Superscalar-Processor-Simulator Public

   A cycle-accurate simulator for an out-of-order superscalar processor that models dynamic instruction scheduling with configurable pipeline width, issue queue size, and reorder buffer capacity.

   C++

6. Xinu-OS-Enhancements Xinu-OS-Enhancements Public

   A collection of system-level enhancements to the Xinu operating system, focusing on core OS functionality including process management, scheduling, and synchronization.

   C