A C++ simulator for L1/L2 cache levels with a configurable stream-buffer prefetch unit, implementing the WBWA policy.
This project implements a configurable cache simulator that can model different levels of memory hierarchy with stream buffer prefetching capabilities. The simulator provides insights into cache performance metrics and memory traffic patterns.
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Configurable Cache Module
- Flexible cache size, associativity, and block size
- Supports multiple cache levels (L1, L2)
- LRU replacement policy
- Write-back and write-allocate policies
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Stream Buffer Prefetching
- Configurable number of stream buffers (N)
- Configurable buffer depth (M blocks per buffer)
- LRU replacement for stream buffers
- Intelligent prefetch stream management
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Memory Hierarchy Configurations
- Single-level cache (L1)
- Two-level cache (L1 + L2)
- Cache with prefetch unit
- Multiple cache levels with prefetch unit
SIZE: Total bytes of data storageASSOC: Cache associativityBLOCKSIZE: Number of bytes per blockPREF_N: Number of stream buffersPREF_M: Blocks per stream buffer
./sim <BLOCKSIZE> <L1_SIZE> <L1_ASSOC> <L2_SIZE> <L2_ASSOC> <PREF_N> <PREF_M> <trace_file>Example:
./sim 32 8192 4 262144 8 3 10 gcc_trace.txt- Cache read/write hits and misses
- Miss rates for each cache level
- Number of writebacks
- Prefetch statistics
- Total memory traffic
Traces follow the format:
r|w <hex address>
r|w <hex address>
...
Where:
- 'r': Read operation
- 'w': Write operation
<hex address>: 32-bit memory address in hex
- Supports power-of-two block sizes
- Implements multi-level cache coherence
- Handles prefetch buffer management
- Tracks LRU information for both cache and stream buffers
- Maintains accurate performance statistics
- C/C++ compiler
- Make build system
- Input trace files
make clean
make- Prepare trace files in correct format
- Run simulator with desired configuration
- Analyze output metrics and cache contents
