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syntax-checks.yaml
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Verilog: split variable and function/task declaration classes Syntactic checks #2977: Pull request #1262 synchronize by kroening
September 12, 2025 20:37 3m 18s verilog_function_declt
verilog_function_declt
September 12, 2025 20:37 3m 18s
Verilog: split variable and function/task declaration classes Syntactic checks #2976: Pull request #1262 opened by kroening
September 12, 2025 14:12 3m 0s verilog_function_declt
verilog_function_declt
September 12, 2025 14:12 3m 0s
Verilog: extract verilog_scopet::identifier_token() Syntactic checks #2975: Pull request #1261 opened by kroening
September 10, 2025 02:48 1m 42s identifier_token
identifier_token
September 10, 2025 02:48 1m 42s
SystemVerilog: create identifier expressions in scanner Syntactic checks #2974: Pull request #953 synchronize by kroening
September 10, 2025 02:27 1m 38s identifier-tokens2
identifier-tokens2
September 10, 2025 02:27 1m 38s
Bump actions/setup-node from 4 to 5 Syntactic checks #2973: Pull request #1260 opened by dependabot bot
September 8, 2025 19:40 2m 10s dependabot/github_actions/actions/setup-node-5
dependabot/github_actions/actions/setup-node-5
September 8, 2025 19:40 2m 10s
Verilog: $isunknown Syntactic checks #2972: Pull request #1149 synchronize by kroening
September 6, 2025 18:02 1m 37s isunknown1
isunknown1
September 6, 2025 18:02 1m 37s
Verilog: module port declarations with default value Syntactic checks #2971: Pull request #1258 synchronize by kroening
September 6, 2025 03:55 1m 40s port_with_value1-fix
port_with_value1-fix
September 6, 2025 03:55 1m 40s
Verilog: module port declarations with default value Syntactic checks #2970: Pull request #1258 synchronize by kroening
September 6, 2025 03:31 2m 8s port_with_value1-fix
port_with_value1-fix
September 6, 2025 03:31 2m 8s
Verilog: module port declarations with default value Syntactic checks #2969: Pull request #1258 synchronize by kroening
September 5, 2025 19:50 3m 15s port_with_value1-fix
port_with_value1-fix
September 5, 2025 19:50 3m 15s
Verilog: module port declarations with default value Syntactic checks #2968: Pull request #1258 synchronize by kroening
September 5, 2025 19:46 1m 36s port_with_value1-fix
port_with_value1-fix
September 5, 2025 19:46 1m 36s
Verilog: strengthen typing in verilog_synthesist::instantiate_ports Syntactic checks #2967: Pull request #1259 synchronize by kroening
September 5, 2025 19:38 2m 35s verilog-synth-port-connection-typing
verilog-synth-port-connection-typing
September 5, 2025 19:38 2m 35s
Verilog: strengthen typing in verilog_synthesist::instantiate_ports Syntactic checks #2966: Pull request #1259 opened by kroening
September 5, 2025 16:58 4m 0s verilog-synth-port-connection-typing
verilog-synth-port-connection-typing
September 5, 2025 16:58 4m 0s
Verilog: module port declarations with default value Syntactic checks #2965: Pull request #1258 synchronize by kroening
September 5, 2025 04:14 3m 24s port_with_value1-fix
port_with_value1-fix
September 5, 2025 04:14 3m 24s
Verilog: module port declarations with default value Syntactic checks #2964: Pull request #1258 synchronize by kroening
September 4, 2025 17:25 6m 22s port_with_value1-fix
port_with_value1-fix
September 4, 2025 17:25 6m 22s
Verilog: module port declarations with default value Syntactic checks #2963: Pull request #1258 opened by kroening
September 4, 2025 14:12 7m 17s port_with_value1-fix
port_with_value1-fix
September 4, 2025 14:12 7m 17s
Verilog: add Verilog type to lowered array type Syntactic checks #2962: Pull request #1257 opened by kroening
September 3, 2025 19:01 2m 19s verilog-array-type
verilog-array-type
September 3, 2025 19:01 2m 19s
Verilog: fix for bit select on boolean argument Syntactic checks #2961: Pull request #1256 opened by kroening
September 2, 2025 22:59 1m 44s index-constant-fix
index-constant-fix
September 2, 2025 22:59 1m 44s
KNOWNBUG test for function in compilation unit scope Syntactic checks #2960: Pull request #1255 opened by kroening
September 2, 2025 04:28 2m 58s compilation_unit_scope_function
compilation_unit_scope_function
September 2, 2025 04:28 2m 58s
Verilog: KNOWNBUG test for conversion of packed array Syntactic checks #2959: Pull request #1253 synchronize by kroening
September 1, 2025 19:20 2m 46s array_conversion1
array_conversion1
September 1, 2025 19:20 2m 46s
Verilog: KNOWNBUG test for module port with value Syntactic checks #2958: Pull request #1254 synchronize by kroening
September 1, 2025 19:19 2m 13s port_with_value1
port_with_value1
September 1, 2025 19:19 2m 13s
Verilog: KNOWNBUG test for module port with value Syntactic checks #2957: Pull request #1254 opened by kroening
September 1, 2025 19:19 2m 10s port_with_value1
port_with_value1
September 1, 2025 19:19 2m 10s
Verilog: KNOWNBUG test for conversion of packed array Syntactic checks #2956: Pull request #1253 opened by kroening
September 1, 2025 19:13 2m 35s array_conversion1
array_conversion1
September 1, 2025 19:13 2m 35s
Verilog: Tests for constant folding of index expressions Syntactic checks #2955: Pull request #1252 opened by kroening
September 1, 2025 16:42 2m 29s index-constant
index-constant
September 1, 2025 16:42 2m 29s
Verilog: reject use of SVA sequences and properties as Boolean expression Syntactic checks #2954: Pull request #1248 synchronize by kroening
August 31, 2025 01:18 1m 35s named_property5-fix
named_property5-fix
August 31, 2025 01:18 1m 35s
$past now supports array and struct types Syntactic checks #2953: Pull request #1247 synchronize by kroening
August 29, 2025 01:38 2m 24s past5-fix
past5-fix
August 29, 2025 01:38 2m 24s