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Verilog: ref port direction #1271

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Merged
merged 2 commits into from
Sep 26, 2025
Merged

Verilog: ref port direction #1271

merged 2 commits into from
Sep 26, 2025

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@kroening
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@kroening kroening commented Sep 24, 2025 •
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SystemVerilog adds the ref port direction, usable for passing a reference to a variable to a module.

@kroening kroening force-pushed the ref1 branch 4 times, most recently from 195e0d0 to 4314098 Compare September 25, 2025 15:56
@kroening
Verilog: use direction field instead of input/output for module_typet
1f31730 
This replaces the boolean input and output fields of the port class by a
single field direction, to enable ref ports.
@kroening kroening changed the title Verilog: ref port type Verilog: ref port direction Sep 26, 2025
@kroening kroening marked this pull request as ready for review September 26, 2025 07:14
tautschnig
tautschnig reviewed Sep 26, 2025
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regression/verilog/modules/ref1.desc Outdated
@@ -0,0 +1,7 @@
KNOWNBUG
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Why is this still KNOWNBUG?

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Fixed

@kroening
Verilog: ref port direction
53d9442 
SystemVerilog adds the ref port direction, usable for passing a reference to
a variable to a module.
@tautschnig tautschnig merged commit d7d19e8 into main Sep 26, 2025
11 checks passed
@tautschnig tautschnig deleted the ref1 branch September 26, 2025 09:38
@kroening kroening mentioned this pull request Oct 19, 2025
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kroening added a commit that referenced this pull request Oct 19, 2025
@kroening
Verilog: fix for port direction of output register ports
418a3bb 
Output register ports are now recognised as outputs.  Fixes a regression
introduced by #1271.

Closes #635.
kroening added a commit that referenced this pull request Oct 19, 2025
@kroening
Verilog: fix for port direction of output register ports
5d77093 
Output register ports are now recognised as outputs.  Fixes a regression
introduced by #1271.

Closes #635.
@kroening kroening mentioned this pull request Oct 19, 2025
Merged
kroening added a commit that referenced this pull request Oct 20, 2025
@kroening
Verilog: fix for port direction of output register ports
1a2ab24 
Output register ports are now recognised as outputs.  Fixes a regression
introduced by #1271.

Closes #635.
kroening added a commit that referenced this pull request Oct 21, 2025
@kroening
Verilog: fix for port direction of output register ports
6503624 
Output register ports are now recognised as outputs.  Fixes a regression
introduced by #1271.

Closes #635.
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@kroening @tautschnig