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Verilog: make power3 test work #1349

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Merged
merged 1 commit into from
Oct 22, 2025
Merged

Verilog: make power3 test work #1349

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3 changes: 1 addition & 2 deletions regression/verilog/expressions/power3.desc
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Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
KNOWNBUG
CORE broken-smt-backend
power3.sv

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
The result is wrong.
8 changes: 4 additions & 4 deletions regression/verilog/expressions/power3.sv
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
module main;

// Any arithmetic with x or z returns x.
initial assert('bx ** 1 === 'x);
initial assert('bz ** 1 === 'x);
initial assert(1 ** 'bx === 'x);
initial assert(1 ** 'bz === 'x);
initial assert('bx ** 1 === 32'hxxxx_xxxx);
initial assert('bz ** 1 === 32'hxxxx_xxxx);
initial assert(1 ** 'bx === 32'hxxxx_xxxx);
initial assert(1 ** 'bz === 32'hxxxx_xxxx);

endmodule
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