Implement scalar Sse2 hardware intrinsics #16237

4creators · 2018-02-06T19:04:16Z

No description provided.

4creators · 2018-02-06T19:06:39Z

src/jit/instrsxarch.h

-INST3( movd,        "movd"        , 0, IUM_WR, 0, 0, PCKDBL(0x7E), BAD_CODE, PCKDBL(0x6E))
-INST3( movq,        "movq"        , 0, IUM_WR, 0, 0, PCKDBL(0xD6), BAD_CODE, SSEFLT(0x7E))
+INST3( movd,        "movd"        , 0, IUM_WR, 0, 0, PCKDBL(0x6E), BAD_CODE, PCKDBL(0xFE)) // Move doubleword from r/m32 to xmm or move doubleword from xmm register to r/m32
+INST3( movq,        "movq"        , 0, IUM_WR, 0, 0, PCKDBL(0xD6), BAD_CODE, SSEFLT(0x7E)) // Move quadword from r/m64 to xmm or move quadword from xmm register to r/m64


Bad merge - will fix

tannergooding · 2018-02-06T19:08:33Z

Just a general nit. It is helpful to break these PRs into two logical commits (one containing the product code changes and one containing the test changes).

The GitHub UI (and even various external code review tools) tend to not do so well with large commits, and making it easier to review the product code is generally desirable (IMO).

tannergooding · 2018-02-06T19:11:52Z

src/jit/emitxarch.cpp

@@ -267,9 +268,12 @@ bool emitter::Is4ByteSSE4Instruction(instruction ins)
 bool emitter::TakesVexPrefix(instruction ins)
 {
    // special case vzeroupper as it requires 2-byte VEX prefix
-    if (ins == INS_vzeroupper)
+    switch (ins)


this seems to be in a weird state. The sfence and prefetch instructions are missing.

Yeah, rebasing to latest head which includes commit containing memory instructions - will fix

tannergooding · 2018-02-06T19:12:39Z

src/jit/emitxarch.cpp

        {
-            return true;
+            case INS_cvttsd2si:


cvttss2si is missing.

Additionally, given that you aren't adding anything new here, it would be generally desirable to move it into its own refactoring PR.

tannergooding · 2018-02-06T19:13:38Z

src/jit/hwintrinsiccodegenxarch.cpp

+            break;
+        }
+
+        case NI_SSE2_CompareEqualOrderedScalar:


These should be merged with the SSE implementations.

Agree, but since there quite a lot refactoring opportunities still coming I have created issue to track this work item #16014 and I plan to work on it once all SSE2 and other similar SSE intrinsics are in.

tannergooding · 2018-02-06T19:15:25Z

src/jit/hwintrinsicxarch.cpp

+            baseType = JITtype2varType(corType);
+
+#ifdef _TARGET_X86_
+            if (varTypeIsLong(JITtype2varType(corType)))


This case should already be handled by impHWIntrinsic

This case should already be handled by impHWIntrinsic

Currently, impHWIntrinsic only handle r64 for return types. Maybe we can make the change latter.

Do we have a bug tracking this yet?

Do we also have any mechanism for determining when the intrinsic takes/returns a 64-bit value but also works on 32-bit machines (there is at least a couple of them)?

Do we have a bug tracking this yet?

I do not think this is a bug. We can introduce more flags to hnit the framework that the intrinsic may have an r64 oprand on first/second/.. position.

Let me make this change after this PR merged.

4creators · 2018-02-06T19:16:32Z

Just a general nit. It is helpful to break these PRs into two logical commits

Do you prefer to break this PR or next ones?

tannergooding · 2018-02-06T19:22:07Z

Do you prefer to break this PR or next ones?

Breaking this one into two should be fairly trivial, since the split is only along a directory:

git fetch --all
git reset --hard dotnet/master
git cherry-pick --no-commit c797d8632e992603e0d5b37d2fb2a130065bf1c7
<resolve conflicts>
git reset
git add src
git commit
git add tests
git commit

fiigii · 2018-02-06T20:19:19Z

src/jit/emitxarch.cpp

+=======
+                           // these are the only ISA extension instructions taking zero operands
+                           || ins == INS_vzeroupper
+>>>>>>> Implement scalar Sse2 hardware intrinsics


Please solve this conflict.

Thanks will fix - next bad merge

fiigii · 2018-02-06T20:24:32Z

src/jit/hwintrinsicxarch.cpp

+            baseType = JITtype2varType(corType);
+
+#ifdef _TARGET_X86_
+            if (varTypeIsLong(JITtype2varType(corType)))


This case should already be handled by impHWIntrinsic

Currently, impHWIntrinsic only handle r64 for return types. Maybe we can make the change latter.

fiigii · 2018-02-06T20:26:57Z

src/jit/hwintrinsicxarch.cpp

+
+            if (baseType == TYP_STRUCT)
+            {
+                baseType = getBaseTypeOfSIMDType(argClass);


I believe that the baseType is always double on Sse2.ConvertScalarToVector128Double.

Yes, that's the case however I try to write code which will be easy to refactor or abstract to handle more cases later see issue #16014. If it is acceptable I would prefer to defer to refactoring PR

Never mind. CVTSS2SD xmm, xmm/m32 and CVTSI2SD xmm, reg/m64 need different encoding.

In this case I use argType as baseType to use it later during instruction emission

fiigii · 2018-02-06T20:29:22Z

src/jit/hwintrinsicxarch.cpp

+            CorInfoType corType =
+                strip(info.compCompHnd->getArgType(sig, argList, &argClass)); // type of the second argument
+
+            baseType = getBaseTypeOfSIMDType(argClass);


The baseType is float (retType's base type) on ConvertScalarToVector128Single.

I need arg types to use correct encoding later (r64 versus r32) during instruction emitting.

Are you talking about ConvertScalarToVector128Double?

Sse2.ConvertScalarToVector128Single just has one signature Vector128<float> ConvertScalarToVector128Single(Vector128<float> upper, Vector128<double> value)

Once I will work on refactoring I will have overloaded - where I need to use second argType as base type
ConvertScalarToVector128Single(Vector128<float> upper, int value)
ConvertScalarToVector128Single(Vector128<float> upper, long value)

If you prefer to simplify it for this PR and not defer changes to refactoring I will do it.

I see. However, I do not think we should combine Sse.ConvertScalarToVector128Single and Sse2.ConvertScalarToVector128Single because they have different signatures and codgen consideration.

Furthermore, combining HW intrinsic code cross-ISA should rely on the current category/flag mechanism rather than "intrinsic names". Meanwhile, a little bit duplicated code is fine to me, it may be not worthwhile to complicate the framework just for a few special cases. We can implement these "special cases" individually, then add categories/flags to combine them if there are some obvious patterns.

OK than I will simplify it and leave any changes during refactoring to the result of discussion of its scope.

fiigii · 2018-02-06T20:30:36Z

src/jit/hwintrinsicxarch.cpp

+            assert(sig->numArgs == 1);
+            op1      = impSIMDPopStack(TYP_SIMD16);
+            retType  = JITtype2varType(sig->retType);
+            baseType = getBaseTypeOfSIMDType(info.compCompHnd->getArgClass(sig, sig->args));


We can directly use the return type as base type.

There are overloads where it is necessary to select different instruction based on argument type - I use baseType to handle this. AFAIR during debugging I have seen problems with baseType detection and that's why I have explicitly recovered it from sig->retType.

Ah, I see there are two special guys

/// <summary> /// int _mm_cvtsd_si32 (__m128d a) /// CVTSD2SI r32, xmm/m64 /// </summary> public static int ConvertToInt32(Vector128<double> value) => ConvertToInt32(value); /// <summary> /// int _mm_cvtsi128_si32 (__m128i a) /// MOVD reg/m32, xmm /// </summary> public static int ConvertToInt32(Vector128<int> value) => ConvertToInt32(value); /// <summary> /// __int64 _mm_cvtsd_si64 (__m128d a) /// CVTSD2SI r64, xmm/m64 /// </summary> public static long ConvertToInt64(Vector128<double> value) => ConvertToInt64(value); /// <summary> /// __int64 _mm_cvtsi128_si64 (__m128i a) /// MOVQ reg/m64, xmm /// </summary> public static long ConvertToInt64(Vector128<long> value) => ConvertToInt64(value);

Perhasps, we can separate these two groups

case NI_SSE2_ConvertToInt32: case NI_SSE2_ConvertToInt64: // get baseType from arg case NI_SSE2_ConvertToUInt32: case NI_SSE2_ConvertToUInt64: // use the return type as base type

because calling getBaseTypeOfSIMDType and info.compCompHnd->getArgClass are relatively expensive

Yeah, you are right. Will fix

4creators · 2018-02-07T20:56:04Z

src/jit/hwintrinsicxarch.cpp

+        case NI_SSE2_ConvertScalarToVector128Int64:
+        case NI_SSE2_ConvertScalarToVector128UInt64:
+        {
+            assert(sig->numArgs == 1);


Due to above I have had to handle above conversion intrinsics as HW_Category_Special

4creators · 2018-02-08T09:32:30Z

@tannergooding There are strange test results. Could you help verify if I should report them as issues to resolve or dig in and look for the reasons myself?

All OSX and Ubuntu stress jobs failed due to the following failure:

A downstream run failed

Miscellaneous build error - see console log for others

D:\j\workspace\checked_windo---2b2fae86\bin\tests\Windows_NT.x64.Checked\TestWrappers\JIT.Performance\JIT.Performance.XUnitWrapper.cs(5777): error : JIT_Performance._CodeQuality_V8_Richards_Richards_Richards_._CodeQuality_V8_Richards_Richards_Richards_cmd [FAIL] [D:\j\workspace\checked_windo---2b2fae86\tests\runtest.proj]

While Windows_NT x64 Checked Build and Test (Jit - EnableIncompleteISAClass=1 FeatureSIMD=0) failure is quite strange:

Test Result (28 failures / +28)
baseservices_exceptions._generics_try_fault_struct01_try_fault_struct01_._generics_try_fault_struct01_try_fault_struct01_cmd
CoreMangLib_cti._system_collections_generic_queueenumerator_EnumeratorCurrent_EnumeratorCurrent_._system_collections_generic_queueenumerator_EnumeratorCurrent_EnumeratorCurrent_cmd
CoreMangLib_cti._system_indexoutofrangeexception_IndexOutOfRangeExceptionctor1_IndexOutOfRangeExceptionctor1_._system_indexoutofrangeexception_IndexOutOfRangeExceptionctor1_IndexOutOfRangeExceptionctor1_cmd
GC_Scenarios._GCSimulator_GCSimulator_300_GCSimulator_300_._GCSimulator_GCSimulator_300_GCSimulator_300_cmd
GC_Scenarios._GCSimulator_GCSimulator_418_GCSimulator_418_._GCSimulator_GCSimulator_418_GCSimulator_418_cmd
GC_Scenarios._GCSimulator_GCSimulator_356_GCSimulator_356_._GCSimulator_GCSimulator_356_GCSimulator_356_cmd
GC_Scenarios._GCSimulator_GCSimulator_342_GCSimulator_342_._GCSimulator_GCSimulator_342_GCSimulator_342_cmd
GC_Scenarios._GCSimulator_GCSimulator_172_GCSimulator_172_._GCSimulator_GCSimulator_172_GCSimulator_172_cmd
GC_Scenarios._GCSimulator_GCSimulator_89_GCSimulator_89_._GCSimulator_GCSimulator_89_GCSimulator_89_cmd
GC_Scenarios._GCSimulator_GCSimulator_58_GCSimulator_58_._GCSimulator_GCSimulator_58_GCSimulator_58_cmd
GC_Scenarios._GCSimulator_GCSimulator_351_GCSimulator_351_._GCSimulator_GCSimulator_351_GCSimulator_351_cmd
GC_Scenarios._GCSimulator_GCSimulator_344_GCSimulator_344_._GCSimulator_GCSimulator_344_GCSimulator_344_cmd
GC_Scenarios._GCSimulator_GCSimulator_162_GCSimulator_162_._GCSimulator_GCSimulator_162_GCSimulator_162_cmd
GC_Scenarios._StringCreator_stringcreator_stringcreator_._StringCreator_stringcreator_stringcreator_cmd
GC_Scenarios._THDChaos_thdchaos_thdchaos_._THDChaos_thdchaos_thdchaos_cmd
GC_Scenarios._GCSimulator_GCSimulator_123_GCSimulator_123_._GCSimulator_GCSimulator_123_GCSimulator_123_cmd
GC_Scenarios._GCSimulator_GCSimulator_397_GCSimulator_397_._GCSimulator_GCSimulator_397_GCSimulator_397_cmd
GC_Scenarios._GCSimulator_GCSimulator_318_GCSimulator_318_._GCSimulator_GCSimulator_318_GCSimulator_318_cmd
GC_Scenarios._GCSimulator_GCSimulator_350_GCSimulator_350_._GCSimulator_GCSimulator_350_GCSimulator_350_cmd
GC_Scenarios._GCSimulator_GCSimulator_141_GCSimulator_141_._GCSimulator_GCSimulator_141_GCSimulator_141_cmd
JIT_HardwareIntrinsics._X86_Sse2_Average_r_Average_r_._X86_Sse2_Average_r_Average_r_cmd
JIT_HardwareIntrinsics._X86_Sse2_UnpackHigh_r_UnpackHigh_r_._X86_Sse2_UnpackHigh_r_UnpackHigh_r_cmd
JIT_jit64._localloc_call_call04_small_call04_small_._localloc_call_call04_small_call04_small_cmd
JIT_Methodical._MDArray_DataTypes_uint_cs_r_uint_cs_r_._MDArray_DataTypes_uint_cs_r_uint_cs_r_cmd
JIT_Performance._CodeQuality_Roslyn_CscBench_CscBench_._CodeQuality_Roslyn_CscBench_CscBench_cmd
JIT_Performance._CodeQuality_Benchstones_BenchF_SqMtx_SqMtx_SqMtx_._CodeQuality_Benchstones_BenchF_SqMtx_SqMtx_SqMtx_cmd
Regressions_coreclr._9414_readonlyPrefix_readonlyPrefix_._9414_readonlyPrefix_readonlyPrefix_cmd
Regressions_coreclr._1549_Test1549_Test1549_._1549_Test1549_Test1549_cmd

tannergooding · 2018-02-08T15:08:24Z

Most of these appear to be Test Infrastructure Failure: The paging file is too small for this operation to complete.

@jkotas, are you aware of any changes that went in recently that could impact this?

jkotas · 2018-02-08T15:58:01Z

No idea what can be causing this.

4creators · 2018-02-09T01:23:12Z

@dotnet-bot test Alpine.3.6 x64 Debug Build please

4creators · 2018-02-09T04:20:23Z

@dotnet-bot test OSX10.12 x64 Checked Innerloop Build and Test please

tannergooding · 2018-02-11T18:08:38Z

src/jit/hwintrinsiccodegenxarch.cpp

            emit->emitIns_SIMD_R_R_R_I(ins, emitTypeSize(TYP_SIMD16), targetReg, op1Reg, op2Reg, ival);

            break;
        }

+        case NI_SSE2_CompareEqualOrderedScalar:


It would be good to have an explicit bug that tracks merging this with the SSE implementation.

The issue #16330 tracks this work item. Could you assign it to me within hardware intrinsics project?

tannergooding · 2018-02-11T18:11:59Z

src/jit/hwintrinsiccodegenxarch.cpp

+            assert(op2 != nullptr);
+            op2Reg          = op2->gtRegNum;
+            instruction ins = Compiler::insOfHWIntrinsic(intrinsicID, baseType);
+            emit->emitIns_SIMD_R_R_R(ins, emitTypeSize(TYP_SIMD16), targetReg, op1Reg, op2Reg);


Can't this one go through genHWIntrinsic_R_R_RM?

tannergooding · 2018-02-11T18:12:22Z

src/jit/hwintrinsiccodegenxarch.cpp

+            assert(op2 != nullptr);
+            op2Reg          = op2->gtRegNum;
+            instruction ins = Compiler::insOfHWIntrinsic(intrinsicID, baseType);
+            emit->emitIns_SIMD_R_R_R(ins, emitTypeSize(TYP_SIMD16), targetReg, op1Reg, op2Reg);


Same here, genHWIntrinsic_R_R_RM?

tannergooding · 2018-02-11T18:13:12Z

src/jit/hwintrinsiccodegenxarch.cpp

+                }
+                else
+                {
+                    emit->emitIns_R_R(INS_mov_xmm2i, emitActualTypeSize(baseType), op1Reg, targetReg);


Why isn't this one using insOfHWIntrinsic?

It's due to #16322 which I plan to fix in #16329

Not sure I follow. We are using INS_mov_xmm2i in both the TYP_LONG and TYP_ULONG case, so it shouldn't matter which base type is used in the lookup...

That is, if only TYP_LONG is being set, we can fill that column of the ConvertToUInt64 table entry with a TODO-XArch-Bug note that it is a workaround.

if only TYP_LONG is being set, we can fill that column of the ConvertToUInt64 table entry with a TODO-XArch-Bug note that it is a workaround

It should be done for TYP_UINT as well. In principle proposed change is equivalent workaround to that used in current code as we always select INS_mov_xmm2i. The workaround currently requires one change but in case we would do it in table we should change instruction selection for multiple intrinsics having unsigned integral base types.

If you agree that current solution is simpler I will add TODO-XArch-Bug comment here.

Looks like this problem is from baseType = JITtype2varType(sig->retType);. We should have a new sign-awared function (e.g., JITtype2BaseVarType, or other name) that only used for HW intrinsics.

We should have a new sign-awared function (e.g., JITtype2BaseVarType, or other name) that only used for HW intrinsics.

Yes, it is tracked by #16329

@tannergooding Could you reply to my comment #16237 (comment)

tannergooding · 2018-02-11T18:15:30Z

src/jit/lsraxarch.cpp

@@ -2283,9 +2283,13 @@ void LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
    switch (intrinsicID)
    {
        case NI_SSE_CompareEqualOrderedScalar:
+        case NI_SSE2_CompareEqualOrderedScalar:


nit: It might be better to keep these grouped as NI_SSE, then NI_SSE2

4creators · 2018-02-11T21:12:57Z

@dotnet-bot test Tizen armel Cross Checked Innerloop Build and Test please

tannergooding · 2018-02-11T21:30:57Z

src/jit/hwintrinsiccodegenxarch.cpp

+            break;
+        }
+
+        case NI_SSE2_ConvertScalarToVector128Single:


nit: This path could be merged with ConvertScalarToVector128Double above. The only difference is the baseType assertion.

tannergooding · 2018-02-11T21:40:33Z

src/jit/hwintrinsicxarch.cpp

+            }
+#endif // _TARGET_X86_
+
+            if (baseType == TYP_STRUCT)


I think we could simplify this to use getArgForHWIntrinsic

Unfortunately, getArgForHWIntrinsic does not handle this logic properly

What about it isn't being handled properly?

It returns TYP_STRUCT instead of TYP_FLOAT - didn't dig deeper to solve it. Plan to have closer look while working on #16329

tannergooding · 2018-02-11T21:43:30Z

Couple more pieces of feedback/questions. Will probably be good for sign-off after the next round.

4creators · 2018-02-12T11:43:39Z

All OSX and Ubuntu jitstress jobs timed out.

4creators · 2018-02-12T15:30:39Z

test Ubuntu x64 Checked jitincompletehwintrinsic
test Ubuntu x64 Checked jitx86hwintrinsicnosimd

4creators · 2018-02-12T15:32:30Z

Again 2 Ubuntu jitstress jobs timeouts

tannergooding · 2018-02-12T15:43:50Z

src/coreclr/hosts/corerun/corerun.cpp

@@ -33,7 +33,7 @@ static const wchar_t *coreCLRDll = W("CoreCLR.dll");
 static const wchar_t *coreCLRInstallDirectory = W("%windir%\\system32\\");

 // Encapsulates the environment that CoreCLR will run in, including the TPALIST
-class HostEnvironment 


This file only contains whitespace changes and isn't related to the PR. It should probably be dropped.

Yes, it is my workflow error, as I use DebugBreak() in corerun.cpp to start debugging and my editor automatically corrects all whitespace errors. Just forgot to undo changes before commit. Will revert.

tannergooding

Overall this LGTM.

It would be good to undo the corerun.cpp changes, since they are unrelated and whitespace changes only.

It would also probably be good (long term) to have explicit comments as to why particular intrinsics aren't/can't be table driven.

4creators · 2018-02-12T16:38:03Z

test Windows_NT x64 Checked jitincompletehwintrinsic
test Windows_NT x64 Checked jitx86hwintrinsicnoavx
test Windows_NT x64 Checked jitx86hwintrinsicnoavx2
test Windows_NT x64 Checked jitx86hwintrinsicnosimd
test Windows_NT x64 Checked jitnox86hwintrinsic

test Windows_NT x86 Checked jitincompletehwintrinsic
test Windows_NT x86 Checked jitx86hwintrinsicnoavx
test Windows_NT x86 Checked jitx86hwintrinsicnoavx2
test Windows_NT x86 Checked jitx86hwintrinsicnosimd
test Windows_NT x86 Checked jitnox86hwintrinsic

test Ubuntu x64 Checked jitincompletehwintrinsic
test Ubuntu x64 Checked jitx86hwintrinsicnoavx
test Ubuntu x64 Checked jitx86hwintrinsicnoavx2
test Ubuntu x64 Checked jitx86hwintrinsicnosimd
test Ubuntu x64 Checked jitnox86hwintrinsic

test OSX10.12 x64 Checked jitincompletehwintrinsic
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx2
test OSX10.12 x64 Checked jitx86hwintrinsicnosimd
test OSX10.12 x64 Checked jitnox86hwintrinsic

CarolEidt

LGTM. Thanks @4creators and also thanks @tannergooding for the reviews!

fiigii

Thank you so much for the work. I logged the PNSE issue at https://github.com/dotnet/coreclr/issues/16342.

4creators · 2018-02-12T21:01:15Z

test Windows_NT x86 Checked jitx86hwintrinsicnosimd

4creators · 2018-02-13T02:42:28Z

test Windows_NT x64 Checked jitx86hwintrinsicnosimd

tannergooding · 2018-02-13T23:08:33Z

Thanks @4creators

4creators commented Feb 6, 2018

View reviewed changes

tannergooding reviewed Feb 6, 2018

View reviewed changes

4creators force-pushed the sse2scalar branch 2 times, most recently from 43bf732 to dc4e7cd Compare February 6, 2018 20:27

fiigii reviewed Feb 6, 2018

View reviewed changes

4creators force-pushed the sse2scalar branch 6 times, most recently from 1b76e1a to b7d95c7 Compare February 7, 2018 20:50

4creators commented Feb 7, 2018

View reviewed changes

4creators force-pushed the sse2scalar branch 2 times, most recently from a7c3f15 to 14fab5b Compare February 8, 2018 01:10

4creators mentioned this pull request Feb 8, 2018

Implement Sse2 memory fence instructions #16262

Merged

4creators mentioned this pull request Feb 8, 2018

Update the table-driven framework to support x86 imm-intrinsics #16183

Merged

4creators force-pushed the sse2scalar branch 2 times, most recently from 8a1c97f to 0f0e6a4 Compare February 9, 2018 01:00

4creators mentioned this pull request Feb 9, 2018

Updating the emitter to more generally handle 4-Byte SSE4 instructions. #16249

Merged

tannergooding reviewed Feb 11, 2018

View reviewed changes

4creators force-pushed the sse2scalar branch 2 times, most recently from 2947cb9 to 8d8ea6b Compare February 11, 2018 19:35

tannergooding reviewed Feb 11, 2018

View reviewed changes

4creators force-pushed the sse2scalar branch from 8d8ea6b to cb767d2 Compare February 12, 2018 00:32

tannergooding reviewed Feb 12, 2018

View reviewed changes

tannergooding approved these changes Feb 12, 2018

View reviewed changes

4creators added 2 commits February 12, 2018 17:10

Implement scalar Sse2 hardware intrinsics

0887ccd

Add Sse2 scalar hardware intrinsics tests

f8fc2fb

4creators force-pushed the sse2scalar branch from cb767d2 to f8fc2fb Compare February 12, 2018 16:11

CarolEidt approved these changes Feb 12, 2018

View reviewed changes

fiigii approved these changes Feb 12, 2018

View reviewed changes

tannergooding merged commit e6d3bd9 into dotnet:master Feb 13, 2018

4creators deleted the sse2scalar branch March 6, 2018 01:01

4creators mentioned this pull request Jan 31, 2020

OSX CI builds are failing during linking of libmscordbi.dylib with missing symbol _IID_ICorDebugFunction4 linker error dotnet/runtime#9695

Closed

fiigii mentioned this pull request Jan 31, 2020

[RyuJIT] Update the table-driven framework to unify throwing PNSE from r64 instructions on 32-bit platform dotnet/runtime#9711

Closed

Implement scalar Sse2 hardware intrinsics #16237

Implement scalar Sse2 hardware intrinsics #16237

Conversation

4creators commented Feb 6, 2018

4creators Feb 6, 2018 • edited Loading

Choose a reason for hiding this comment

tannergooding commented Feb 6, 2018

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

4creators Feb 6, 2018 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

4creators commented Feb 6, 2018

tannergooding commented Feb 6, 2018 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

fiigii Feb 6, 2018 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

fiigii Feb 6, 2018 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

fiigii Feb 6, 2018 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

fiigii Feb 6, 2018 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

4creators commented Feb 8, 2018

tannergooding commented Feb 8, 2018

jkotas commented Feb 8, 2018

4creators commented Feb 9, 2018

4creators commented Feb 9, 2018

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

fiigii Feb 11, 2018 • edited Loading

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

4creators commented Feb 11, 2018

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

Choose a reason for hiding this comment

tannergooding commented Feb 11, 2018

4creators commented Feb 12, 2018

4creators commented Feb 12, 2018

4creators commented Feb 12, 2018

Choose a reason for hiding this comment

Choose a reason for hiding this comment

tannergooding left a comment

Choose a reason for hiding this comment

4creators commented Feb 12, 2018

CarolEidt left a comment

Choose a reason for hiding this comment

4creators Feb 6, 2018 •

edited

Loading

4creators Feb 6, 2018 •

edited

Loading

tannergooding commented Feb 6, 2018 •

edited

Loading

fiigii Feb 6, 2018 •

edited

Loading

fiigii Feb 6, 2018 •

edited

Loading

fiigii Feb 6, 2018 •

edited

Loading

fiigii Feb 6, 2018 •

edited

Loading

fiigii Feb 11, 2018 •

edited

Loading