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Enable the accelerated instructions for conversion for X86
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@khushal1996
khushal1996 committed Mar 8, 2024
1 parent 2367f40 commit 07f6b77
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Showing 4 changed files with 25 additions and 29 deletions.
4 changes: 2 additions & 2 deletions src/coreclr/jit/compiler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3172,7 +3172,7 @@ class Compiler
GenTree* op3,
CorInfoType simdBaseJitType,
unsigned simdSize);
#if defined(TARGET_AMD64)
#if defined(TARGET_XARCH)
GenTree* gtNewSimdCvtNode(var_types type,
GenTree* op1,
NamedIntrinsic hwIntrinsicID,
Expand All @@ -3184,7 +3184,7 @@ class Compiler
var_types sourceType,
var_types targetType,
unsigned simdSize);
#endif //TARGET_AMD64
#endif //TARGET_XARCH
GenTree* gtNewSimdCreateBroadcastNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);

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29 changes: 20 additions & 9 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21251,7 +21251,7 @@ GenTree* Compiler::gtNewSimdCeilNode(var_types type, GenTree* op1, CorInfoType s
return gtNewSimdHWIntrinsicNode(type, op1, intrinsic, simdBaseJitType, simdSize);
}

#if defined(TARGET_AMD64)
#if defined(TARGET_XARCH)
GenTreeVecCon* Compiler::gtCvtCtrlTbl(var_types type, var_types sourceType, var_types targetType, unsigned simdSize)
{
assert(IsBaselineSimdIsaSupportedDebugOnly());
Expand Down Expand Up @@ -21350,13 +21350,24 @@ GenTree* Compiler::gtNewSimdCvtNode(var_types type,

if (varTypeIsSigned(simdTargetBaseType))
{
ssize_t actualMaxVal = (varTypeIsInt(simdTargetBaseType)) ? INT32_MAX : INT64_MAX;

GenTree* maxVal = gtNewDconNode(static_cast<double>(actualMaxVal), simdSourceBaseType);

maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize);
GenTree* maxValDup = gtNewSimdCreateBroadcastNode(type, gtNewIconNode(actualMaxVal, simdTargetBaseType),
simdTargetBaseJitType, simdSize);
GenTree* maxVal;
GenTree* maxValDup;
if (varTypeIsLong(simdTargetBaseType))
{
long long actualMaxVal = INT64_MAX;
maxVal = gtNewDconNode(static_cast<double>(actualMaxVal), simdSourceBaseType);
maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize);
maxValDup =
gtNewSimdCreateBroadcastNode(type, gtNewLconNode(actualMaxVal), simdTargetBaseJitType, simdSize);
}
else
{
ssize_t actualMaxVal = INT32_MAX;
maxVal = gtNewDconNode(static_cast<double>(actualMaxVal), simdSourceBaseType);
maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize);
maxValDup = gtNewSimdCreateBroadcastNode(type, gtNewIconNode(actualMaxVal, simdTargetBaseType),
simdTargetBaseJitType, simdSize);
}

// we will be using the input value twice
GenTree* fixupValDup = fgMakeMultiUse(&fixupVal);
Expand All @@ -21375,7 +21386,7 @@ GenTree* Compiler::gtNewSimdCvtNode(var_types type,
return gtNewSimdHWIntrinsicNode(type, fixupVal, hwIntrinsicID, simdSourceBaseJitType, simdSize);
}
}
#endif // TARGET_AMD64
#endif // TARGET_XARCH

GenTree* Compiler::gtNewSimdCmpOpNode(
genTreeOps op, var_types type, GenTree* op1, GenTree* op2, CorInfoType simdBaseJitType, unsigned simdSize)
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9 changes: 1 addition & 8 deletions src/coreclr/jit/hwintrinsicxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1446,7 +1446,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
op1 = impSIMDPopStack();
Expand All @@ -1457,7 +1456,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,

retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_LONG, simdBaseJitType, simdSize);
}
#endif
break;
}

Expand All @@ -1467,7 +1465,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
op1 = impSIMDPopStack();
Expand All @@ -1477,7 +1474,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,

retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_UINT, simdBaseJitType, simdSize);
}
#endif
#
break;
}

Expand All @@ -1487,7 +1484,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
op1 = impSIMDPopStack();
Expand All @@ -1497,7 +1493,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,

retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_ULONG, simdBaseJitType, simdSize);
}
#endif
break;
}

Expand All @@ -1507,7 +1502,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
op1 = impSIMDPopStack();
Expand All @@ -1517,7 +1511,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,

retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_INT, simdBaseJitType, simdSize);
}
#endif
break;
}

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12 changes: 2 additions & 10 deletions src/coreclr/jit/simdashwintrinsic.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -532,12 +532,12 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
case NI_VectorT_ConvertToUInt32:
case NI_VectorT_ConvertToUInt64:
{
#ifdef TARGET_AMD64
#ifdef TARGET_XARCH
if (IsBaselineVector512IsaSupportedOpportunistically())
{
break;
}
#endif // TARGET_AMD64
#endif // TARGET_XARCH
return nullptr;
}

Expand Down Expand Up @@ -1181,7 +1181,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
NamedIntrinsic intrinsic =
Expand All @@ -1191,15 +1190,13 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,

return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_LONG, simdBaseJitType, simdSize);
}
#endif
return nullptr;
}

case NI_VectorT_ConvertToUInt32:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
NamedIntrinsic intrinsic =
Expand All @@ -1209,15 +1206,13 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,

return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_UINT, simdBaseJitType, simdSize);
}
#endif
return nullptr;
}

case NI_VectorT_ConvertToUInt64:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
NamedIntrinsic intrinsic =
Expand All @@ -1227,14 +1222,12 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,

return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_ULONG, simdBaseJitType, simdSize);
}
#endif
return nullptr;
}

case NI_VectorT_ConvertToInt32:
{
assert(simdBaseType == TYP_FLOAT);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
NamedIntrinsic intrinsic =
Expand All @@ -1244,7 +1237,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,

return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_INT, simdBaseJitType, simdSize);
}
#endif
return nullptr;
}

Expand Down

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