Skip to content

Commit

Permalink
[Arm64] AddAcross MaxAcross MinAcross MaxNumber MaxNumberPairwise Max…
Browse files Browse the repository at this point in the history 
…Pairwise (#32620)

Implements the following intrinsics: 

* AddPairwise, AddPairwiseScalar

* MaxAcross

* MaxNumber, MaxNumberScalar

* MaxNumberAcross

* MaxPairwise, MaxPairwiseScalar

* MinAcross

* MinNumberAcross

* MinPairwise, MinPairwiseScalar

---

Updates AddAcross to return Vector64<T> as we discussed in API review meeting

---

Updates emitter such that emitIns functions for faddp (scalar), fmaxp (scalar), fmaxv, smaxv and similar instructions require opt argument to have non-INS_OPTS_NONE value (i.e. specified according to the Arm technical documentation even in a case when an instruction has only one valid vector arrangement). For example, 2-operand form of faddp requires INS_OPTS_2S or INS_OPTS_2D options to be specified and fmaxv requires INS_OPTS_4S.

---

Changes the precedence of criteria for computing instruction SIMD size for GT_HWINTRINSIC node. This is needed for AddAcross, MaxAcross, AddPairwiseScalar etc.

For example, AddPairwiseScalar returns Vector64<T> value and before that change the SIMD size computed here was based only on the return value size (even when BaseTypeFromFirstArg or BaseTypeFromSecondArg flags were set), i.e. it was 8 bytes in all of these cases:

* Vector64<float> AddAcross(Vector128<float> value) - SIMD size should be 16 bytes FADDV Sd, Vn.4S

* Vector64<float> AddPairwiseScalar (Vector64<float> value) - SIMD size is 8 bytes FADDP Sd, Vn.2S

* Vector64<double> AddPairwiseScalar (Vector128<double> value) - SIMD size should be 16 bytes FADDP Dd, Vn.2D

---

Moves smaxv, sminv, addv and similar instructions to a separate instruction form DV_2T.
  • Loading branch information
@echesakov
echesakov authored Feb 21, 2020
1 parent 58cf146 commit 9981b1f
Show file tree
Hide file tree
Showing 727 changed files with 54,577 additions and 825 deletions.
41 changes: 19 additions & 22 deletions src/coreclr/src/jit/codegenarm64.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4516,13 +4516,13 @@ void CodeGen::genSIMDIntrinsicDotProduct(GenTreeSIMD* simdNode)
{
if (opt == INS_OPTS_4S)
{
GetEmitter()->emitIns_R_R_R(INS_faddp, attr, tmpReg, tmpReg, tmpReg, INS_OPTS_4S);
GetEmitter()->emitIns_R_R_R(INS_faddp, EA_16BYTE, tmpReg, tmpReg, tmpReg, INS_OPTS_4S);
}
GetEmitter()->emitIns_R_R(INS_faddp, EA_4BYTE, targetReg, tmpReg, INS_OPTS_2S);
GetEmitter()->emitIns_R_R(INS_faddp, EA_8BYTE, targetReg, tmpReg, INS_OPTS_2S);
}
else
{
GetEmitter()->emitIns_R_R(INS_faddp, EA_8BYTE, targetReg, tmpReg, INS_OPTS_2D);
GetEmitter()->emitIns_R_R(INS_faddp, EA_16BYTE, targetReg, tmpReg, INS_OPTS_2D);
}
}
else
Expand Down Expand Up @@ -6893,32 +6893,32 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_fabs, EA_16BYTE, REG_V8, REG_V9, INS_OPTS_2D);

// fmaxp scalar
theEmitter->emitIns_R_R(INS_fmaxp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fmaxp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
theEmitter->emitIns_R_R(INS_fmaxp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fmaxp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fmaxnmp scalar
theEmitter->emitIns_R_R(INS_fmaxnmp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fmaxnmp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
theEmitter->emitIns_R_R(INS_fmaxnmp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fmaxnmp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fmaxnmv vector
theEmitter->emitIns_R_R(INS_fmaxnmv, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_fmaxnmv, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_4S);

// fmaxv vector
theEmitter->emitIns_R_R(INS_fmaxv, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_fmaxv, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_4S);

// fminp vector
theEmitter->emitIns_R_R(INS_fminp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fminp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
// fminp scalar
theEmitter->emitIns_R_R(INS_fminp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fminp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fminnmp scalar
theEmitter->emitIns_R_R(INS_fminnmp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fminnmp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
theEmitter->emitIns_R_R(INS_fminnmp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fminnmp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fminnmv vector
theEmitter->emitIns_R_R(INS_fminnmv, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_fminnmv, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_4S);

// fminv vector
theEmitter->emitIns_R_R(INS_fminv, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_fminv, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_4S);

// fneg scalar
theEmitter->emitIns_R_R(INS_fneg, EA_4BYTE, REG_V0, REG_V1);
Expand Down Expand Up @@ -7023,15 +7023,13 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_addv, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_addv, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_addv, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_addv, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_addv, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);

// saddlv vector
theEmitter->emitIns_R_R(INS_saddlv, EA_8BYTE, REG_V4, REG_V5, INS_OPTS_8B);
theEmitter->emitIns_R_R(INS_saddlv, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_saddlv, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_saddlv, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_saddlv, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_saddlv, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);

// smaxv vector
Expand All @@ -7053,7 +7051,6 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_uaddlv, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_uaddlv, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_uaddlv, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_uaddlv, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_uaddlv, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);

// umaxv vector
Expand All @@ -7071,8 +7068,8 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_uminv, EA_16BYTE, REG_V12, REG_V13, INS_OPTS_4S);

// faddp scalar
theEmitter->emitIns_R_R(INS_faddp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_faddp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
theEmitter->emitIns_R_R(INS_faddp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_faddp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// INS_fcvtl
theEmitter->emitIns_R_R(INS_fcvtl, EA_4BYTE, REG_V0, REG_V1);
Expand Down Expand Up @@ -7575,7 +7572,7 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R_R(INS_add, EA_16BYTE, REG_V21, REG_V22, REG_V23, INS_OPTS_2D);

// addp
theEmitter->emitIns_R_R(INS_addp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2D); // scalar 8BYTE
theEmitter->emitIns_R_R(INS_addp, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_2D); // scalar 16BYTE
theEmitter->emitIns_R_R_R(INS_addp, EA_8BYTE, REG_V3, REG_V4, REG_V5, INS_OPTS_8B);
theEmitter->emitIns_R_R_R(INS_addp, EA_8BYTE, REG_V6, REG_V7, REG_V8, INS_OPTS_4H);
theEmitter->emitIns_R_R_R(INS_addp, EA_8BYTE, REG_V9, REG_V10, REG_V11, INS_OPTS_2S);
Expand Down
79 changes: 45 additions & 34 deletions src/coreclr/src/jit/emitarm64.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -732,33 +732,42 @@ void emitter::emitInsSanityCheck(instrDesc* id)

case IF_DV_2Q: // DV_2Q .........X...... ......nnnnnddddd Sd Vn (faddp, fmaxnmp, fmaxp, fminnmp,
// fminp - scalar)
if (id->idOpSize() == EA_8BYTE)
if (id->idOpSize() == EA_16BYTE)
{
assert(id->idInsOpt() == INS_OPTS_2D);
}
else
{
assert(id->idOpSize() == EA_4BYTE);
assert(id->idOpSize() == EA_8BYTE);
assert(id->idInsOpt() == INS_OPTS_2S);
}
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2R: // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
assert(id->idOpSize() == EA_4BYTE);
assert(id->idOpSize() == EA_16BYTE);
assert(id->idInsOpt() == INS_OPTS_4S);
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2S: // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
assert(id->idOpSize() == EA_8BYTE);
assert(id->idOpSize() == EA_16BYTE);
assert(id->idInsOpt() == INS_OPTS_2D);
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2T: // DV_2T .Q......XX...... ......nnnnnddddd Sd Vn (addv, saddlv, smaxv, sminv, uaddlv,
// umaxv, uminv)
assert(isValidVectorDatasize(id->idOpSize()));
elemsize = optGetElemsize(id->idInsOpt());
assert((elemsize != EA_8BYTE) && (id->idInsOpt() != INS_OPTS_2S)); // can't use 2D or 1D or 2S
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_3A: // DV_3A .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
Expand Down Expand Up @@ -2085,6 +2094,7 @@ emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt)
case IF_DV_2O:
case IF_DV_2P:
case IF_DV_2R:
case IF_DV_2T:
case IF_DV_3A:
case IF_DV_3AI:
case IF_DV_3B:
Expand Down Expand Up @@ -4071,6 +4081,14 @@ void emitter::emitIns_R_R(
case INS_uaddlv:
case INS_umaxv:
case INS_uminv:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
assert(isValidVectorDatasize(size));
assert(isValidArrangement(size, opt));
assert((opt != INS_OPTS_2S) && (opt != INS_OPTS_1D) && (opt != INS_OPTS_2D)); // Reserved encodings
fmt = IF_DV_2T;
break;

case INS_rev64:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
Expand Down Expand Up @@ -4345,7 +4363,7 @@ void emitter::emitIns_R_R(
case INS_fminnmp:
case INS_fminp:
// Scalar operation
assert(((size == EA_4BYTE) && (opt == INS_OPTS_2S)) || ((size == EA_8BYTE) && (opt == INS_OPTS_2D)));
assert(((size == EA_8BYTE) && (opt == INS_OPTS_2S)) || ((size == EA_16BYTE) && (opt == INS_OPTS_2D)));
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
fmt = IF_DV_2Q;
Expand All @@ -4355,15 +4373,15 @@ void emitter::emitIns_R_R(
case INS_fmaxv:
case INS_fminnmv:
case INS_fminv:
assert(size == EA_4BYTE);
assert(size == EA_16BYTE);
assert(opt == INS_OPTS_4S);
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
fmt = IF_DV_2R;
break;

case INS_addp:
assert(size == EA_8BYTE);
assert(size == EA_16BYTE);
assert(opt == INS_OPTS_2D);
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
Expand Down Expand Up @@ -10075,6 +10093,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
break;

case IF_DV_2A: // DV_2A .Q.......X...... ......nnnnnddddd Vd Vn (fabs, fcvt - vector)
case IF_DV_2R: // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
elemsize = optGetElemsize(id->idInsOpt());
code = emitInsCode(ins, fmt);
code |= insEncodeVectorsize(id->idOpSize()); // Q
Expand Down Expand Up @@ -10156,8 +10175,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
break;

case IF_DV_2G: // DV_2G .........X...... ......nnnnnddddd Vd Vn (fmov, fcvtXX - register)
case IF_DV_2Q: // DV_2Q .........X...... ......nnnnnddddd Vd Vn (faddp, fmaxnmp, fmaxp, fminnmp,
// fminp - scalar)
elemsize = id->idOpSize();
code = emitInsCode(ins, fmt);
code |= insEncodeFloatElemsize(elemsize); // X
Expand Down Expand Up @@ -10202,7 +10219,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
break;

case IF_DV_2L: // DV_2L ........XX...... ......nnnnnddddd Vd Vn (abs, neg - scalar)
case IF_DV_2S: // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
elemsize = id->idOpSize();
code = emitInsCode(ins, fmt);
code |= insEncodeElemsize(elemsize); // XX
Expand All @@ -10212,6 +10228,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
break;

case IF_DV_2M: // DV_2M .Q......XX...... ......nnnnnddddd Vd Vn (abs, neg - vector)
case IF_DV_2T: // DV_2T .Q......XX...... ......nnnnnddddd Sd Vn (addv, saddlv, smaxv, sminv, uaddlv,
// umaxv, uminv)
elemsize = optGetElemsize(id->idInsOpt());
code = emitInsCode(ins, fmt);
code |= insEncodeVectorsize(id->idOpSize()); // Q
Expand Down Expand Up @@ -10249,17 +10267,25 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
dst += emitOutput_Instr(dst, code);
break;

case IF_DV_2R: // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
code = emitInsCode(ins, fmt);
datasize = optGetDatasize(id->idInsOpt());
case IF_DV_2Q: // DV_2Q .........X...... ......nnnnnddddd Vd Vn (faddp, fmaxnmp, fmaxp, fminnmp,
// fminp - scalar)
elemsize = optGetElemsize(id->idInsOpt());
code |= insEncodeVectorsize(datasize); // Q
code = emitInsCode(ins, fmt);
code |= insEncodeFloatElemsize(elemsize); // X
code |= insEncodeReg_Vd(id->idReg1()); // ddddd
code |= insEncodeReg_Vn(id->idReg2()); // nnnnn
dst += emitOutput_Instr(dst, code);
break;

case IF_DV_2S: // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
elemsize = optGetElemsize(id->idInsOpt());
code = emitInsCode(ins, fmt);
code |= insEncodeElemsize(elemsize); // XX
code |= insEncodeReg_Vd(id->idReg1()); // ddddd
code |= insEncodeReg_Vn(id->idReg2()); // nnnnn
dst += emitOutput_Instr(dst, code);
break;

case IF_DV_3A: // DV_3A .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
code = emitInsCode(ins, fmt);
elemsize = optGetElemsize(id->idInsOpt());
Expand Down Expand Up @@ -11672,25 +11698,8 @@ void emitter::emitDispIns(
break;

case IF_DV_2M: // DV_2M .Q......XX...... ......nnnnnddddd Vd Vn (abs, neg - vector)
switch (ins)
{
case INS_addv:
case INS_saddlv:
case INS_smaxv:
case INS_sminv:
case INS_uaddlv:
case INS_umaxv:
case INS_uminv:
elemsize = optGetElemsize(id->idInsOpt());
emitDispReg(id->idReg1(), elemsize, true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
break;

default:
emitDispVectorReg(id->idReg1(), id->idInsOpt(), true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
break;
}
emitDispVectorReg(id->idReg1(), id->idInsOpt(), true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
break;

case IF_DV_2N: // DV_2N .........iiiiiii ......nnnnnddddd Vd Vn imm (shift - scalar)
Expand Down Expand Up @@ -11812,7 +11821,9 @@ void emitter::emitDispIns(
// fminp - scalar)
case IF_DV_2R: // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
case IF_DV_2S: // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
elemsize = id->idOpSize();
case IF_DV_2T: // DV_2T .Q......XX...... ......nnnnnddddd Sd Vn (addv, saddlv, smaxv, sminv, uaddlv,
// umaxv, uminv)
elemsize = optGetElemsize(id->idInsOpt());
emitDispReg(id->idReg1(), elemsize, true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
break;
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/src/jit/emitfmtsarm64.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -199,6 +199,7 @@ IF_DEF(DV_2P, IS_NONE, NONE) // DV_2P ................ ......nnnnnddddd V
IF_DEF(DV_2Q, IS_NONE, NONE) // DV_2Q .........X...... ......nnnnnddddd Sd Vn (faddp, fmaxnmp, fmaxp, fminnmp, fminp - scalar)
IF_DEF(DV_2R, IS_NONE, NONE) // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
IF_DEF(DV_2S, IS_NONE, NONE) // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
IF_DEF(DV_2T, IS_NONE, NONE) // DV_2T .Q......XX...... ......nnnnnddddd Sd Vn (addv, saddlv, smaxv, sminv, uaddlv, umaxv, uminv)

IF_DEF(DV_3A, IS_NONE, NONE) // DV_3A .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
IF_DEF(DV_3AI, IS_NONE, NONE) // DV_3AI .Q......XXLMmmmm ....H.nnnnnddddd Vd Vn Vm[] (vector by elem)
Expand Down
14 changes: 7 additions & 7 deletions src/coreclr/src/jit/hwintrinsic.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -247,20 +247,20 @@ unsigned HWIntrinsicInfo::lookupSimdSize(Compiler* comp, NamedIntrinsic id, CORI

CORINFO_CLASS_HANDLE typeHnd = nullptr;

if (JITtype2varType(sig->retType) == TYP_STRUCT)
{
typeHnd = sig->retTypeSigClass;
}
else if (HWIntrinsicInfo::BaseTypeFromFirstArg(id))
if (HWIntrinsicInfo::BaseTypeFromFirstArg(id))
{
typeHnd = comp->info.compCompHnd->getArgClass(sig, sig->args);
}
else
else if (HWIntrinsicInfo::BaseTypeFromSecondArg(id))
{
assert(HWIntrinsicInfo::BaseTypeFromSecondArg(id));
CORINFO_ARG_LIST_HANDLE secondArg = comp->info.compCompHnd->getArgNext(sig->args);
typeHnd = comp->info.compCompHnd->getArgClass(sig, secondArg);
}
else
{
assert(JITtype2varType(sig->retType) == TYP_STRUCT);
typeHnd = sig->retTypeSigClass;
}

unsigned simdSize = 0;
var_types baseType = comp->getBaseTypeAndSizeOfSIMDType(typeHnd, &simdSize);
Expand Down
Loading

0 comments on commit 9981b1f

Please sign in to comment.