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[NativeAOT/ARM64] Generate frames compatible with Apple compact unwinding #111451
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…ding (dotnet#107766) * JIT/ARM64: Add ability to generate frames compatible with Apple compact unwinding format. For NativeAOT/ARM64/Apple API do the following: - Save callee registers in opposite order and in pairs. - Prefer saving FP/LR on the top of the frame. Heuristics are used to avoid worse code quality outside of prolog/epilog due to addressing range limits of the ARM64 instruction set. - Added optimization to lvaFrameAddress to rewrite FP-x references to SP+y when possible. This allows efficient addressing using positive indexes when FP points to the top of the frame. It mimics similar optimization on ARM32. * ObjWriter: For Mach-O ARM64 try to convert the DWARF CFI unwinding codes into compact unwinding code * Disable lvaFrameAddress FP->SP optimization for OSR methods
FP-n => SP+m (for m = frameSize - n) optimization.
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
/azp list |
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/azp run runtime-coreclr outerloop, runtime-coreclr jitstress, runtime-coreclr gcstress0x3-gcstress0xc, runtime-coreclr gcstress-extra |
Azure Pipelines successfully started running 4 pipeline(s). |
Outerloop failures seem unrelated |
The win-x86 failure is #109500. We should reopen the issue. |
Can we open a separate issue? It does not look like the same crash symptom to me (different platform, unhandled managed exception vs AV). |
Platform is different, but the pipeline is not and neither is the test... Notably, the linked issue was already mixing both osx-arm64 and linux-arm. Log from the PR:
Linked issue:
|
Ah nevermind, there is an unhandled exception in the log. |
Can we (re-)merge this? /cc @kunalspathak |
ofs2Dist = EA_SIZE_IN_BYTES(size); | ||
#ifdef DEBUG | ||
assert(FPbased == FPbased2); | ||
if (FPbased) | ||
{ | ||
assert(id->idReg3() == REG_FP); |
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i forgot to ask, but why this assert was removed?
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The optimization in lvaFrameAddress
can rewrite FP-n expression to SP+m in the instruction encoding which would be one of the inputs here. Since here we call lvaFrameAddress
again with an additional parameter that suppresses this optimization (to always get FP-relative offset for purpose of GC info offset for something that was FP-relative in the first place), we can can get a mismatch. This mismatch is expected.
(The general idea of the optimization is that in the instruction encoding we can substitute the two because they refer to the same memory location and positive offsets have wider range that can be expressed in the instruction encoding. For the GC info offsets we want to use the original offsets due to the way how GC info is encoded. This closely matches the same logic in ARM32.)
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LGTM
…ct unwinding (dotnet#111451)" This reverts commit 9031940.
Re-introduces original commit 4536b96 (PR #107766) which was reverted with bbe2cb9 (PR #111405).
The additional commit fixes the issue with GC info in GC stress. It uses the same approach as ARM32 where
lvaFrameAddress
has an a new parameter to suppress the FP-n => SP+m optimization when we are calculating the offsets for GC info purposes.