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[Arm64] ASIMD InsertScalar and rename to ShiftLeftAndInsert ShiftRightAndInsert #38680

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merged 13 commits into from
Jul 2, 2020
Merged

[Arm64] ASIMD InsertScalar and rename to ShiftLeftAndInsert ShiftRightAndInsert #38680

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885d0d6
Add InsertScalar in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Jun 26, 2020
8c9807b
Update System.Runtime.Intrinsics.cs
echesakov Jun 26, 2020
386b1a5
Update Vector128.WithLower and Vector128.WithUpper to use InsertScala…
echesakov Jun 26, 2020
0dc578f
Add InsertScalarTest.template and add InsertScalar in GenerateTests.csx
echesakov Jun 26, 2020
a1283d9
Implement InsertScalar in JIT
echesakov Jun 27, 2020
b1e2aa3
Update AdvSimd/
echesakov Jul 1, 2020
6232a26
Rename ShiftLeftLogicalAndInsert->ShiftLeftAndInsert, ShiftLeftLogica…
echesakov Jul 1, 2020
6236e48
Rename ShiftLeftLogicalAndInsert->ShiftLeftAndInsert, ShiftLeftLogica…
echesakov Jul 1, 2020
7b6add4
Re-order ShiftLeftAndInsert and ShiftRightAndInsert in AdvSimd.cs Adv…
echesakov Jul 1, 2020
6352a6b
Update System.Runtime.Intrinsics.cs
echesakov Jul 1, 2020
9c7d3b9
Update GenerateTests.csx
echesakov Jul 1, 2020
02f5347
Update Helpers.cs Helpers.tt
echesakov Jul 1, 2020
9fc108a
Update AdvSimd/
echesakov Jul 1, 2020
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5 changes: 3 additions & 2 deletions src/coreclr/src/jit/hwintrinsic.cpp
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Expand Up @@ -807,7 +807,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
sigReader.Read(info.compCompHnd, sig);

#ifdef TARGET_ARM64
if ((intrinsic == NI_AdvSimd_Insert) || (intrinsic == NI_AdvSimd_LoadAndInsertScalar))
if ((intrinsic == NI_AdvSimd_Insert) || (intrinsic == NI_AdvSimd_InsertScalar) ||
(intrinsic == NI_AdvSimd_LoadAndInsertScalar))
{
assert(sig->numArgs == 3);
immOp = impStackTop(1).val;
Expand Down Expand Up @@ -1058,7 +1059,7 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
}
}
}
else if (intrinsic == NI_AdvSimd_Insert)
else if ((intrinsic == NI_AdvSimd_Insert) || (intrinsic == NI_AdvSimd_InsertScalar))
{
op2 = addRangeCheckIfNeeded(intrinsic, op2, mustExpand, immLowerBound, immUpperBound);
}
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/src/jit/hwintrinsicarm64.cpp
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Expand Up @@ -225,6 +225,7 @@ void HWIntrinsicInfo::lookupImmBounds(
case NI_AdvSimd_ExtractVector128:
case NI_AdvSimd_ExtractVector64:
case NI_AdvSimd_Insert:
case NI_AdvSimd_InsertScalar:
case NI_AdvSimd_LoadAndInsertScalar:
case NI_AdvSimd_StoreSelectedScalar:
case NI_AdvSimd_Arm64_DuplicateSelectedScalarToVector128:
Expand Down
21 changes: 21 additions & 0 deletions src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -644,6 +644,27 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
}
break;

case NI_AdvSimd_InsertScalar:
{
assert(isRMW);
assert(targetReg != op3Reg);

if (targetReg != op1Reg)
{
GetEmitter()->emitIns_R_R(INS_mov, emitTypeSize(node), targetReg, op1Reg);
}

HWIntrinsicImmOpHelper helper(this, intrin.op2, node);

for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
{
const int elementIndex = helper.ImmValue();

GetEmitter()->emitIns_R_R_I_I(ins, emitSize, targetReg, op3Reg, elementIndex, 0, opt);
}
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}
break;

case NI_AdvSimd_Arm64_InsertSelectedScalar:
{
assert(isRMW);
Expand Down
7 changes: 4 additions & 3 deletions src/coreclr/src/jit/hwintrinsiclistarm64.h
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Expand Up @@ -165,6 +165,7 @@ HARDWARE_INTRINSIC(AdvSimd, FusedMultiplySubtractScalar,
HARDWARE_INTRINSIC(AdvSimd, FusedMultiplySubtractNegatedScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fnmsub, INS_fnmsub}, HW_Category_SIMD, HW_Flag_SIMDScalar|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AdvSimd, FusedSubtractHalving, -1, 2, {INS_shsub, INS_uhsub, INS_shsub, INS_uhsub, INS_shsub, INS_uhsub, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, Insert, -1, 3, {INS_ins, INS_ins, INS_ins, INS_ins, INS_ins, INS_ins, INS_ins, INS_ins, INS_ins, INS_ins}, HW_Category_SIMD, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar|HW_Flag_SpecialCodeGen|HW_Flag_SupportsContainment)
HARDWARE_INTRINSIC(AdvSimd, InsertScalar, 16, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ins, INS_ins, INS_invalid, INS_ins}, HW_Category_SIMD, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AdvSimd, LeadingSignCount, -1, 1, {INS_cls, INS_invalid, INS_cls, INS_invalid, INS_cls, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, LeadingZeroCount, -1, 1, {INS_clz, INS_clz, INS_clz, INS_clz, INS_clz, INS_clz, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, LoadAndInsertScalar, -1, 3, {INS_ld1, INS_ld1, INS_ld1, INS_ld1, INS_ld1, INS_ld1, INS_ld1, INS_ld1, INS_ld1, INS_ld1}, HW_Category_MemoryLoad, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar|HW_Flag_SpecialCodeGen)
Expand Down Expand Up @@ -235,9 +236,9 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticRoundedScalar,
HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticSaturate, -1, 2, {INS_sqshl, INS_invalid, INS_sqshl, INS_invalid, INS_sqshl, INS_invalid, INS_sqshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sqshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftAndInsert, -1, 3, {INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sli, INS_sli, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogical, -1, 2, {INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalAndInsert, -1, 3, {INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sli, INS_sli, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturate, -1, 2, {INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateUnsigned, -1, 2, {INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftLeftByImmediate, HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand)
Expand All @@ -254,7 +255,7 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalSaturate,
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_uqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushl, INS_ushl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightAndInsert, -1, 3, {INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sri, INS_sri, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sri, INS_sri, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmetic, -1, 2, {INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAdd, -1, 3, {INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAddScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/src/jit/lowerarmarch.cpp
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Expand Up @@ -1416,6 +1416,7 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
case NI_AdvSimd_DuplicateSelectedScalarToVector64:
case NI_AdvSimd_DuplicateSelectedScalarToVector128:
case NI_AdvSimd_Extract:
case NI_AdvSimd_InsertScalar:
case NI_AdvSimd_LoadAndInsertScalar:
case NI_AdvSimd_Arm64_DuplicateSelectedScalarToVector128:
case NI_Vector64_GetElement:
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/src/jit/lsraarm64.cpp
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Expand Up @@ -1025,6 +1025,7 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
case NI_AdvSimd_DuplicateSelectedScalarToVector128:
case NI_AdvSimd_Extract:
case NI_AdvSimd_Insert:
case NI_AdvSimd_InsertScalar:
case NI_AdvSimd_LoadAndInsertScalar:
case NI_AdvSimd_Arm64_DuplicateSelectedScalarToVector128:
needBranchTargetReg = !intrin.op2->isContainedIntOrIImmed();
Expand Down
6 changes: 3 additions & 3 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part2_r.csproj
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Expand Up @@ -60,6 +60,9 @@
<Compile Include="Insert.Vector128.UInt16.1.cs" />
<Compile Include="Insert.Vector128.UInt32.1.cs" />
<Compile Include="Insert.Vector128.UInt64.1.cs" />
<Compile Include="InsertScalar.Vector128.Double.1.cs" />
<Compile Include="InsertScalar.Vector128.Int64.1.cs" />
<Compile Include="InsertScalar.Vector128.UInt64.1.cs" />
<Compile Include="LeadingSignCount.Vector64.Int16.cs" />
<Compile Include="LeadingSignCount.Vector64.Int32.cs" />
<Compile Include="LeadingSignCount.Vector64.SByte.cs" />
Expand Down Expand Up @@ -261,9 +264,6 @@
<Compile Include="MultiplyBySelectedScalar.Vector128.UInt16.Vector128.UInt16.7.cs" />
<Compile Include="MultiplyBySelectedScalar.Vector128.UInt32.Vector64.UInt32.1.cs" />
<Compile Include="MultiplyBySelectedScalar.Vector128.UInt32.Vector128.UInt32.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int16.Vector64.Int16.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int16.Vector128.Int16.7.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int32.Vector64.Int32.1.cs" />
<Compile Include="Program.AdvSimd_Part2.cs" />
<Compile Include="..\Shared\Helpers.cs" />
<Compile Include="..\Shared\Program.cs" />
Expand Down
6 changes: 3 additions & 3 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part2_ro.csproj
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Expand Up @@ -60,6 +60,9 @@
<Compile Include="Insert.Vector128.UInt16.1.cs" />
<Compile Include="Insert.Vector128.UInt32.1.cs" />
<Compile Include="Insert.Vector128.UInt64.1.cs" />
<Compile Include="InsertScalar.Vector128.Double.1.cs" />
<Compile Include="InsertScalar.Vector128.Int64.1.cs" />
<Compile Include="InsertScalar.Vector128.UInt64.1.cs" />
<Compile Include="LeadingSignCount.Vector64.Int16.cs" />
<Compile Include="LeadingSignCount.Vector64.Int32.cs" />
<Compile Include="LeadingSignCount.Vector64.SByte.cs" />
Expand Down Expand Up @@ -261,9 +264,6 @@
<Compile Include="MultiplyBySelectedScalar.Vector128.UInt16.Vector128.UInt16.7.cs" />
<Compile Include="MultiplyBySelectedScalar.Vector128.UInt32.Vector64.UInt32.1.cs" />
<Compile Include="MultiplyBySelectedScalar.Vector128.UInt32.Vector128.UInt32.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int16.Vector64.Int16.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int16.Vector128.Int16.7.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int32.Vector64.Int32.1.cs" />
<Compile Include="Program.AdvSimd_Part2.cs" />
<Compile Include="..\Shared\Helpers.cs" />
<Compile Include="..\Shared\Program.cs" />
Expand Down
6 changes: 3 additions & 3 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part3_r.csproj
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Expand Up @@ -8,6 +8,9 @@
<Optimize />
</PropertyGroup>
<ItemGroup>
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int16.Vector64.Int16.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int16.Vector128.Int16.7.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int32.Vector64.Int32.1.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int32.Vector128.Int32.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.UInt16.Vector64.UInt16.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.UInt16.Vector128.UInt16.7.cs" />
Expand Down Expand Up @@ -261,9 +264,6 @@
<Compile Include="ShiftArithmeticRounded.Vector128.Int32.cs" />
<Compile Include="ShiftArithmeticRounded.Vector128.Int64.cs" />
<Compile Include="ShiftArithmeticRounded.Vector128.SByte.cs" />
<Compile Include="ShiftArithmeticRoundedSaturate.Vector64.Int16.cs" />
<Compile Include="ShiftArithmeticRoundedSaturate.Vector64.Int32.cs" />
<Compile Include="ShiftArithmeticRoundedSaturate.Vector64.SByte.cs" />
<Compile Include="Program.AdvSimd_Part3.cs" />
<Compile Include="..\Shared\Helpers.cs" />
<Compile Include="..\Shared\Program.cs" />
Expand Down
6 changes: 3 additions & 3 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part3_ro.csproj
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Expand Up @@ -8,6 +8,9 @@
<Optimize>True</Optimize>
</PropertyGroup>
<ItemGroup>
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int16.Vector64.Int16.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int16.Vector128.Int16.7.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int32.Vector64.Int32.1.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.Int32.Vector128.Int32.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.UInt16.Vector64.UInt16.3.cs" />
<Compile Include="MultiplyBySelectedScalarWideningLower.Vector64.UInt16.Vector128.UInt16.7.cs" />
Expand Down Expand Up @@ -261,9 +264,6 @@
<Compile Include="ShiftArithmeticRounded.Vector128.Int32.cs" />
<Compile Include="ShiftArithmeticRounded.Vector128.Int64.cs" />
<Compile Include="ShiftArithmeticRounded.Vector128.SByte.cs" />
<Compile Include="ShiftArithmeticRoundedSaturate.Vector64.Int16.cs" />
<Compile Include="ShiftArithmeticRoundedSaturate.Vector64.Int32.cs" />
<Compile Include="ShiftArithmeticRoundedSaturate.Vector64.SByte.cs" />
<Compile Include="Program.AdvSimd_Part3.cs" />
<Compile Include="..\Shared\Helpers.cs" />
<Compile Include="..\Shared\Program.cs" />
Expand Down
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