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Generate proper DWARF reg num for ARM32 #57443

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merged 3 commits into from
Aug 16, 2021
Merged

Generate proper DWARF reg num for ARM32 #57443

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0d074e6
Generate proper DWARF reg num for ARM32
kant2002 Aug 15, 2021
498e739
Rearrange code as per suggestions from PR
kant2002 Aug 16, 2021
7f2b453
Fix formatting
kant2002 Aug 16, 2021
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7 changes: 6 additions & 1 deletion src/coreclr/jit/unwind.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -187,7 +187,12 @@ void Compiler::unwindPushPopMaskCFI(regMaskTP regMask, bool isFloat)
regMaskTP regBit = isFloat ? genRegMask(REG_FP_FIRST) : 1;

for (regNumber regNum = isFloat ? REG_FP_FIRST : REG_FIRST; regNum < REG_COUNT;
regNum = REG_NEXT(regNum), regBit <<= 1)
#if TARGET_ARM
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For better readability, I would rewrite this to. I would add a short comment for why we need to do special case for ARM.

regNumber regNum = isFloat ? REG_FP_FIRST : REG_FIRST;
for (; regNum < REG_COUNT;)
{
#if TARGET_ARM
    regNum = isFloat ? REG_NEXT(REG_NEXT(regNum)) : REG_NEXT(regNum);
    regBit <<= isFloat ? 2 : 1;
#else
    regNum = REG_NEXT(regNum);
    regBit <<= 1;
#endregion
...
...
}

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Done!

regNum = isFloat ? REG_NEXT(REG_NEXT(regNum)) : REG_NEXT(regNum), regBit <<= isFloat ? 2 : 1
#else
regNum = REG_NEXT(regNum), regBit <<= 1
#endif
)
{
if (regBit > regMask)
{
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80 changes: 16 additions & 64 deletions src/coreclr/jit/unwindarm.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -71,100 +71,52 @@ short Compiler::mapRegNumToDwarfReg(regNumber reg)
dwarfReg = 15;
break;
case REG_F0:
dwarfReg = 64;
break;
case REG_F1:
dwarfReg = 65;
dwarfReg = 256;
break;
case REG_F2:
dwarfReg = 66;
break;
case REG_F3:
dwarfReg = 67;
dwarfReg = 257;
break;
case REG_F4:
dwarfReg = 68;
break;
case REG_F5:
dwarfReg = 69;
dwarfReg = 258;
break;
case REG_F6:
dwarfReg = 70;
break;
case REG_F7:
dwarfReg = 71;
dwarfReg = 259;
break;
case REG_F8:
dwarfReg = 72;
break;
case REG_F9:
dwarfReg = 73;
dwarfReg = 260;
break;
case REG_F10:
dwarfReg = 74;
break;
case REG_F11:
dwarfReg = 75;
dwarfReg = 261;
break;
case REG_F12:
dwarfReg = 76;
break;
case REG_F13:
dwarfReg = 77;
dwarfReg = 262;
break;
case REG_F14:
dwarfReg = 78;
break;
case REG_F15:
dwarfReg = 79;
dwarfReg = 263;
break;
case REG_F16:
dwarfReg = 80;
break;
case REG_F17:
dwarfReg = 81;
dwarfReg = 264;
break;
case REG_F18:
dwarfReg = 82;
break;
case REG_F19:
dwarfReg = 83;
dwarfReg = 265;
break;
case REG_F20:
dwarfReg = 84;
break;
case REG_F21:
dwarfReg = 85;
dwarfReg = 266;
break;
case REG_F22:
dwarfReg = 86;
break;
case REG_F23:
dwarfReg = 87;
dwarfReg = 267;
break;
case REG_F24:
dwarfReg = 88;
break;
case REG_F25:
dwarfReg = 89;
dwarfReg = 268;
break;
case REG_F26:
dwarfReg = 90;
break;
case REG_F27:
dwarfReg = 91;
dwarfReg = 269;
break;
case REG_F28:
dwarfReg = 92;
break;
case REG_F29:
dwarfReg = 93;
dwarfReg = 270;
break;
case REG_F30:
dwarfReg = 94;
break;
case REG_F31:
dwarfReg = 95;
dwarfReg = 271;
break;
default:
noway_assert(!"unexpected REG_NUM");
Expand Down