[JIT] X64 - Using cmovns for faster division

src/coreclr/jit/codegen.h

@@ -780,6 +780,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void genLeaInstruction(GenTreeAddrMode* lea);
     void genSetRegToCond(regNumber dstReg, GenTree* tree);
 
+#ifdef TARGET_AMD64
+    void genCodeForDivCnsPow2(GenTreeOp* treeNode);
+#endif // TARGET_AMD64
+
 #if defined(TARGET_ARMARCH) || defined(TARGET_LOONGARCH64)
     void genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale);
 #endif // TARGET_ARMARCH || TARGET_LOONGARCH64

src/coreclr/jit/codegenxarch.cpp

@@ -806,6 +806,15 @@ void CodeGen::genCodeForDivMod(GenTreeOp* treeNode)
 {
     assert(treeNode->OperIs(GT_DIV, GT_UDIV, GT_MOD, GT_UMOD));
 
+#ifdef TARGET_AMD64
+    if (treeNode->OperIs(GT_DIV) && treeNode->gtGetOp2()->isContained() &&
+        treeNode->gtGetOp2()->IsIntegralConstAbsPow2())
+    {
+        genCodeForDivCnsPow2(treeNode);
+        return;
+    }
+#endif // TARGET_AMD64
+
     GenTree* dividend = treeNode->gtOp1;
 
 #ifdef TARGET_X86
@@ -873,6 +882,54 @@ void CodeGen::genCodeForDivMod(GenTreeOp* treeNode)
     genProduceReg(treeNode);
 }
 
+#ifdef TARGET_AMD64
+//------------------------------------------------------------------------
+// genCodeForDivCnsPow2: Generate code for a DIV with a divisor that is a constant power of two.
+//
+// Arguments:
+//    treeNode - the node to generate the code for
+//
+void CodeGen::genCodeForDivCnsPow2(GenTreeOp* treeNode)
+{
+    assert(treeNode->OperIs(GT_DIV));
+
+    GenTree* dividend = treeNode->gtOp1;
+
+    GenTree*  divisor    = treeNode->gtOp2;
+    emitAttr  size       = emitTypeSize(treeNode);
+    regNumber targetReg  = treeNode->GetRegNum();
+    var_types targetType = treeNode->TypeGet();
+    emitter*  emit       = GetEmitter();
+
+    assert(varTypeIsIntOrI(targetType));
+    assert(divisor->IsIntegralConstAbsPow2());
+    assert(divisor->isContained());
+
+    genConsumeOperands(treeNode);
+
+    regNumber dividendReg = dividend->GetRegNum();
+
+    const ssize_t cnsDivisor    = divisor->AsIntConCommon()->IntegralValue();
+    const size_t  absCnsDivisor = abs(cnsDivisor);
+
+    assert(absCnsDivisor != 2);
+    assert(dividendReg != targetReg);
+
+    emit->emitIns_R_AR(INS_lea, size, targetReg, dividendReg, static_cast<int>(absCnsDivisor - 1));
+    emit->emitIns_R_R(INS_test, size, dividendReg, dividendReg);
+    emit->emitIns_R_R(INS_cmovns, size, targetReg, dividendReg);
+
+    emit->emitIns_R_I(INS_sar_N, size, targetReg, genLog2(static_cast<size_t>(absCnsDivisor)));
+
+    if (cnsDivisor < 0)
+    {
+        emit->emitIns_R(INS_neg, size, targetReg);
+    }
+
+    genProduceReg(treeNode);
+}
+#endif // TARGET_AMD64
+
 //------------------------------------------------------------------------
 // genCodeForBinary: Generate code for many binary arithmetic operators
 //

src/coreclr/jit/lower.cpp

@@ -6123,6 +6123,14 @@ GenTree* Lowering::LowerConstIntDivOrMod(GenTree* node)
     LIR::Use opDividend(BlockRange(), &divMod->AsOp()->gtOp1, divMod);
     dividend = ReplaceWithLclVar(opDividend);
 
+#ifdef TARGET_AMD64
+    if (comp->opts.OptimizationEnabled() && isDiv && (absDivisorValue >= 4))
+    {
+        MakeSrcContained(divMod, divisor);
+        return divMod->gtNext;
+    }
+#endif // TARGET_AMD64
+
     GenTree* adjustment = comp->gtNewOperNode(GT_RSH, type, dividend, comp->gtNewIconNode(type == TYP_INT ? 31 : 63));
 
     if (absDivisorValue == 2)

src/coreclr/jit/lsraxarch.cpp

@@ -1781,6 +1781,16 @@ int LinearScan::BuildModDiv(GenTree* tree)
         return BuildSimple(tree);
     }
 
+#ifdef TARGET_AMD64
+    if (tree->OperIs(GT_DIV) && op2->isContained() && op2->IsIntegralConstAbsPow2())
+    {
+        srcCount = BuildDelayFreeUses(tree->gtGetOp1());
+        buildInternalRegisterUses();
+        BuildDef(tree);
+        return 1;
+    }
+#endif // TARGET_AMD64
+
     // Amd64 Div/Idiv instruction:
     //    Dividend in RAX:RDX  and computes
     //    Quotient in RAX, Remainder in RDX