Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Remove dead code in lookupScheme2 #7134

Merged
merged 1 commit into from
Oct 13, 2023
Merged

Remove dead code in lookupScheme2 #7134

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
157 changes: 48 additions & 109 deletions compiler/p/codegen/ControlFlowEvaluator.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1290,17 +1290,17 @@ static TR::Register *compareLongsForOrderWithAnalyser(TR::InstOpCode::Mnemonic b
TR::ILOpCodes firstOp = firstChild->getOpCodeValue();
if (firstChild->getReferenceCount() == 1 && src1Reg == NULL)
{
if (firstOp == TR::iu2l || firstOp == TR::su2l ||
(firstOp == TR::lushr &&
firstChild->getSecondChild()->getOpCode().isLoadConst() &&
(firstChild->getSecondChild()->getInt() & LONG_SHIFT_MASK) == 32))
{
firstChild = firstChild->getFirstChild();
if (firstOp == TR::lushr)
{
firstUseHighOrder = true;
}
}
if (firstOp == TR::iu2l || firstOp == TR::su2l ||
(firstOp == TR::lushr &&
firstChild->getSecondChild()->getOpCode().isLoadConst() &&
(firstChild->getSecondChild()->getInt() & LONG_SHIFT_MASK) == 32))
{
firstChild = firstChild->getFirstChild();
if (firstOp == TR::lushr)
{
firstUseHighOrder = true;
}
}
}
}

Expand All @@ -1310,17 +1310,17 @@ static TR::Register *compareLongsForOrderWithAnalyser(TR::InstOpCode::Mnemonic b
TR::ILOpCodes secondOp = secondChild->getOpCodeValue();
if (secondChild->getReferenceCount() == 1 && src2Reg == NULL)
{
if (secondOp == TR::iu2l || secondOp == TR::su2l ||
(secondOp == TR::lushr &&
secondChild->getSecondChild()->getOpCode().isLoadConst() &&
(secondChild->getSecondChild()->getInt() & LONG_SHIFT_MASK) == 32))
{
secondChild = secondChild->getFirstChild();
if (secondOp == TR::lushr)
{
secondUseHighOrder = true;
}
}
if (secondOp == TR::iu2l || secondOp == TR::su2l ||
(secondOp == TR::lushr &&
secondChild->getSecondChild()->getOpCode().isLoadConst() &&
(secondChild->getSecondChild()->getInt() & LONG_SHIFT_MASK) == 32))
{
secondChild = secondChild->getFirstChild();
if (secondOp == TR::lushr)
{
secondUseHighOrder = true;
}
}
}
}

Expand Down Expand Up @@ -1378,7 +1378,7 @@ static TR::Register *compareLongsForOrderWithAnalyser(TR::InstOpCode::Mnemonic b
{
src2Low = src2Reg->getHighOrder();
}
else
else
{
src2Low = src2Reg->getLowOrder();
}
Expand Down Expand Up @@ -1508,11 +1508,11 @@ TR::Register *OMR::Power::TreeEvaluator::compareLongsForOrder(TR::InstOpCode::Mn
TR::RegisterDependencyConditions *deps = NULL;

if ((firstChild->isHighWordZero() || secondChild->isHighWordZero()) &&
!(secondChild->getOpCode().isLoadConst() &&
secondChild->getRegister() == NULL))
{
return compareLongsForOrderWithAnalyser(branchOp, reversedBranchOp, condReg, dstLabel, deps, node, cg, isHint, likeliness);
}
!(secondChild->getOpCode().isLoadConst() &&
secondChild->getRegister() == NULL))
{
return compareLongsForOrderWithAnalyser(branchOp, reversedBranchOp, condReg, dstLabel, deps, node, cg, isHint, likeliness);
}

TR::Register *src2Reg;
src1Reg = cg->evaluate(firstChild);
Expand All @@ -1533,7 +1533,7 @@ TR::Register *OMR::Power::TreeEvaluator::compareLongsForOrder(TR::InstOpCode::Mn
}

if (deps == NULL)
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(4, 4, cg->trMemory());
deps = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(4, 4, cg->trMemory());

fixDepsForLongCompare(deps, src1Reg->getHighOrder(), src1Reg->getLowOrder(), useImmed ? NULL : src2Reg->getHighOrder(), useImmed ? NULL : src2Reg->getLowOrder());
TR::PPCControlFlowInstruction *cfop = (TR::PPCControlFlowInstruction *)
Expand Down Expand Up @@ -3693,19 +3693,19 @@ static void lookupScheme1(TR::Node *node, bool unbalanced, bool fromTableEval, T
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::cmpi4, node, cndRegister, selector, fromTableEval?(i-2):(int32_t)(child->getCaseConstant()));
}
if (unbalanced)
{
{
bcond = conditions;
if (child->getNumChildren() > 0)
{
{
cg->evaluate(child->getFirstChild());
bcond = bcond->clone(cg, generateRegisterDependencyConditions(cg, child->getFirstChild(), 0));
}
}
generateDepConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, child->getBranchDestination()->getNode()->getLabel(), cndRegister, bcond);
}
}
else
{
{
generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, child->getBranchDestination()->getNode()->getLabel(), cndRegister);
}
}
}

if (two_reg)
Expand All @@ -3727,43 +3727,18 @@ static void lookupScheme2(TR::Node *node, bool unbalanced, bool fromTableEval, T
TR::Register *cndRegister = cg->allocateRegister(TR_CCR);
TR::Register *valRegister = NULL;

bool isInt64 = false;
bool two_reg = (cg->comp()->target().is32Bit()) && isInt64;
TR::LabelSymbol *toDefaultLabel = NULL;
if ( two_reg )
{
valRegister = cg->allocateRegisterPair(cg->allocateRegister(),cg->allocateRegister());
toDefaultLabel = generateLabelSymbol(cg);
}
else
{
valRegister = cg->allocateRegister();
}
valRegister = cg->allocateRegister();

TR::RegisterDependencyConditions *acond, *bcond, *conditions = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(5, 5, cg->trMemory());
TR::Node *secondChild = node->getSecondChild();

if(two_reg)
{
TR::addDependency(conditions, valRegister->getHighOrder(), TR::RealRegister::NoReg, TR_GPR, cg);
TR::addDependency(conditions, valRegister->getLowOrder(), TR::RealRegister::NoReg, TR_GPR, cg);
TR::addDependency(conditions, selector->getHighOrder(), TR::RealRegister::NoReg, TR_GPR, cg);
TR::addDependency(conditions, selector->getLowOrder(), TR::RealRegister::NoReg, TR_GPR, cg);
}
else
{
TR::addDependency(conditions, valRegister, TR::RealRegister::NoReg, TR_GPR, cg);
TR::addDependency(conditions, selector, TR::RealRegister::NoReg, TR_GPR, cg);
}
TR::addDependency(conditions, valRegister, TR::RealRegister::NoReg, TR_GPR, cg);
TR::addDependency(conditions, selector, TR::RealRegister::NoReg, TR_GPR, cg);

TR::addDependency(conditions, cndRegister, TR::RealRegister::NoReg, TR_CCR, cg);
conditions->getPreConditions()->getRegisterDependency(0)->setExcludeGPR0();
conditions->getPostConditions()->getRegisterDependency(0)->setExcludeGPR0();
if(two_reg)
{
conditions->getPreConditions()->getRegisterDependency(1)->setExcludeGPR0();
conditions->getPostConditions()->getRegisterDependency(1)->setExcludeGPR0();
}

acond = conditions;
if (secondChild->getNumChildren()>0 && !unbalanced)
Expand All @@ -3774,72 +3749,36 @@ static void lookupScheme2(TR::Node *node, bool unbalanced, bool fromTableEval, T

int32_t preInt = fromTableEval?0:node->getChild(2)->getCaseConstant();

if (isInt64)
{
if (two_reg)
{
loadConstant(cg, node, (int32_t)(preInt >> 32), valRegister->getHighOrder());
loadConstant(cg, node, (int32_t)preInt, valRegister->getLowOrder());
}
else
loadConstant(cg, node, preInt, valRegister);
}
else
{
loadConstant(cg, node, (int32_t) preInt, valRegister);
}
loadConstant(cg, node, preInt, valRegister);

for (int i=2; i<total; i++)
{
TR::Node *child = node->getChild(i);

if (isInt64)
{
if (cg->comp()->target().is64Bit())
{
generateTrg1Src2Instruction(cg, TR::InstOpCode::cmp8, node, cndRegister, selector, valRegister);
}
else
{
generateTrg1Src2Instruction(cg, TR::InstOpCode::cmp4, node, cndRegister, selector->getHighOrder(), valRegister->getHighOrder());
generateConditionalBranchInstruction(cg, TR::InstOpCode::bne, node, toDefaultLabel, cndRegister);
generateTrg1Src2Instruction(cg, TR::InstOpCode::cmp4, node, cndRegister, selector->getLowOrder(), valRegister->getLowOrder());
}
}
else
{
generateTrg1Src2Instruction(cg, TR::InstOpCode::cmp4, node, cndRegister, selector, valRegister);
}
generateTrg1Src2Instruction(cg, TR::InstOpCode::cmp4, node, cndRegister, selector, valRegister);

if (unbalanced)
{
{
bcond = conditions;
if (child->getNumChildren() > 0)
{
{
cg->evaluate(child->getFirstChild());
bcond = bcond->clone(cg, generateRegisterDependencyConditions(cg, child->getFirstChild(), 0));
}
}
generateDepConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, child->getBranchDestination()->getNode()->getLabel(), cndRegister, bcond);
}
}
else
{
{
generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, child->getBranchDestination()->getNode()->getLabel(), cndRegister);
}
}
if (i<total-1)
{
{
int32_t diff = fromTableEval?1:(node->getChild(i+1)->getCaseConstant()-preInt);
preInt += diff;
if (!isInt64)
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi2, node, valRegister, valRegister, (int32_t)diff);
else
addConstantToLong(node, valRegister, diff, valRegister, cg);

generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi2, node, valRegister, valRegister, (int32_t)diff);
}
}

if (two_reg)
generateLabelInstruction(cg, TR::InstOpCode::label, node, toDefaultLabel);

if (secondChild->getNumChildren()>0 && unbalanced)
{
cg->evaluate(secondChild->getFirstChild());
Expand Down