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Most issues
Fewest issues
blocker
blocker
Something isn't working and no workaround
deferred
deferred
Deferred until after current Redesign Project
5
dependencies
dependencies
Pull requests that update a dependency file
1
documentation
documentation
Improvements or additions to documentation
10
duplicate
duplicate
This issue or pull request already exists
ECO
ECO
Engineering change order (post-PnR)
enhancement
enhancement
New feature or request
9
error
error
Something isn't working
6
flow
flow
Makefile or in-repository flow script changed
10
good first issue
good first issue
Good for newcomers
help wanted
help wanted
Extra attention is needed
invalid
invalid
This doesn't seem right
packaging
packaging
1
PnR
PnR
Gate level verilog and/or layout changed
7
precheck
precheck
Issues related to precheck
question
question
Further information is requested
1
RTL
RTL
Verilog source code changed
6
SDC
SDC
Added or changed timing files
1
signoff
signoff
simulation
simulation
Verilog testbenches and simulation
1
wontfix
wontfix
This will not be worked on
wrong repo
wrong repo
Error is in a different repository