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frontend/etherbone: Add 1-Slot PacketFIFO on LiteEthEtherboneProbe to prevent deadlock situation. #94

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merged 1 commit into from
Nov 9, 2021

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enjoy-digital
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@enjoy-digital enjoy-digital commented Nov 8, 2021

Based on @david-sawatzke's analysis:
"Otherwise, depending on the caching in the path, a deadlock might occur due to the rx path being
blocked by the tx path, being blocked by the arp request, for which the answers get dropped in the
rx path."

… prevent deadlock situation.

Based on @BASED on @david-sawatzke's analysis:
"Otherwise, depending on the caching in the path, a deadlock might occur due to the rx path being
blocked by the tx path, being blocked by the arp request, for which the answers get dropped in the
rx path."
@david-sawatzke
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I've tested this and #93 on the colorlight 5a-75b, but compared to a few days ago now after a few lines of the bios crossterm print on the ROM line, a response packet gets lost and litex_server hangs completely. After restarting litex_server & litex_term, the console output continues as expected. Maybe my USB 3.0 gigabit ethernet adapter is interfering, but I doubt it.

Unfortunately this doesn't occur in simulation, so I can't (easily) find out what goes wrong.

The behaviour of both PRs seems to be completely identical and both regs & ident work without issue.

@enjoy-digital enjoy-digital merged commit 4dd95ea into master Nov 9, 2021
@enjoy-digital
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Thanks @david-sawatzke, I'm merging it and will also do more testing.

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2 participants