examples: simplify using add_csr

enjoy-digital · Dec 2, 2019 · 607397a · 607397a
1 parent a41508e
commit 607397a
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Showing 4 changed files with 6 additions and 27 deletions.
diff --git a/examples/targets/bist.py b/examples/targets/bist.py
@@ -64,10 +64,6 @@ def __init__(self, platform, sata_phys):
 
 class BISTSoC(SoCMini):
     default_platform = "kc705"
-    csr_map = {
-        "sata_bist": 16
-    }
-    csr_map.update(SoCMini.csr_map)
     def __init__(self, platform, revision="sata_gen3", data_width=16):
         clk_freq = int(200e6)
         SoCMini.__init__(self, platform, clk_freq,
@@ -90,6 +86,7 @@ def __init__(self, platform, revision="sata_gen3", data_width=16):
         self.submodules.sata_core     = LiteSATACore(self.sata_phy)
         self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
         self.submodules.sata_bist     = LiteSATABIST(self.sata_crossbar, with_csr=True)
+        self.add_csr("sata_bist")
 
         # Status Leds ------------------------------------------------------------------------------
         self.submodules.leds = StatusLeds(platform, self.sata_phy)
@@ -112,10 +109,6 @@ def __init__(self, platform, revision="sata_gen3", data_width=16):
 # BISTSoCDevel -------------------------------------------------------------------------------------
 
 class BISTSoCDevel(BISTSoC):
-    csr_map = {
-        "analyzer": 17
-    }
-    csr_map.update(BISTSoC.csr_map)
     def __init__(self, platform):
         from litescope import LiteScopeAnalyzer
         BISTSoC.__init__(self, platform)
@@ -135,5 +128,6 @@ def __init__(self, platform):
             self.sata_core.command.tx.fsm,
         ]
         self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 2048, csr_csv="test/analyzer.csv")
+        self.add_csr("analyzer")
 
 default_subtarget = BISTSoC
diff --git a/examples/targets/bist_nexys_video.py b/examples/targets/bist_nexys_video.py
@@ -88,10 +88,6 @@ def __init__(self, platform, sata_phys):
 
 class BISTSoC(SoCMini):
     default_platform = "kc705"
-    csr_map = {
-        "sata_bist": 16
-    }
-    csr_map.update(SoCMini.csr_map)
     def __init__(self, platform, revision="sata_gen2", data_width=16):
         sys_clk_freq = int(100e6)
         SoCMini.__init__(self, platform, sys_clk_freq,
@@ -114,6 +110,7 @@ def __init__(self, platform, revision="sata_gen2", data_width=16):
         self.submodules.sata_core     = LiteSATACore(self.sata_phy)
         self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
         self.submodules.sata_bist     = LiteSATABIST(self.sata_crossbar, with_csr=True)
+        self.add_csr("sata_bist")
 
         # Status Leds ------------------------------------------------------------------------------
         self.submodules.leds = StatusLeds(platform, self.sata_phy)
@@ -136,10 +133,6 @@ def __init__(self, platform, revision="sata_gen2", data_width=16):
 # BISTSoCDevel -------------------------------------------------------------------------------------
 
 class BISTSoCDevel(BISTSoC):
-    csr_map = {
-        "analyzer": 17
-    }
-    csr_map.update(BISTSoC.csr_map)
     def __init__(self, platform):
         from litescope import LiteScopeAnalyzer
         BISTSoC.__init__(self, platform)
@@ -161,5 +154,6 @@ def __init__(self, platform):
             self.sata_core.command.tx.fsm,
         ]
         self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 256, csr_csv="test/analyzer.csv")
+        self.add_csr("analyzer")
 
 default_subtarget = BISTSoCDevel
diff --git a/examples/targets/mirroring.py b/examples/targets/mirroring.py
@@ -20,13 +20,6 @@
 
 class MirroringSoC(SoCMini):
     default_platform = "kc705"
-    csr_map = {
-        "sata_bist0": 16,
-        "sata_bist1": 17,
-        "sata_bist2": 18,
-        "sata_bist3": 19,
-    }
-    csr_map.update(SoCMini.csr_map)
     def __init__(self, platform, revision="sata_gen3", data_width=16, nphys=4):
         self.nphys = nphys
         clk_freq = 200*1000000
@@ -75,6 +68,7 @@ def __init__(self, platform, revision="sata_gen3", data_width=16, nphys=4):
             sata_bist = LiteSATABIST(self.sata_crossbars[i], with_csr=True)
             setattr(self.submodules, "sata_bist{}".format(str(i)), sata_bist)
             self.sata_bists.append(sata_bist)
+            self.add_csr("sata_bist" + str(i))
 
         # Status Leds ------------------------------------------------------------------------------
         self.submodules.status_leds = StatusLeds(platform, self.sata_phys)

diff --git a/examples/targets/striping.py b/examples/targets/striping.py
@@ -20,10 +20,6 @@
 
 class StripingSoC(SoCMini):
     default_platform = "kc705"
-    csr_map = {
-        "sata_bist": 16
-    }
-    csr_map.update(SoCMini.csr_map)
     def __init__(self, platform, revision="sata_gen3", data_width=16, nphys=4):
         self.nphys = nphys
         clk_freq = 200*1000000
@@ -65,6 +61,7 @@ def __init__(self, platform, revision="sata_gen3", data_width=16, nphys=4):
 
         # SATA Application -------------------------------------------------------------------------
         self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
+        self.add_csr("sata_bist")
 
         # Status Leds ------------------------------------------------------------------------------
         self.submodules.status_leds = StatusLeds(platform, self.sata_phys)