tools/litex_sim support for remote_bitbang (openocd)

[Dolu1990]

This PR mostly merge previously made work to add jtagremote support into litex_sim.py

Here is a simple way to test it :

Terminal 1 :

litex_sim --cpu-type=vexriscv_smp --with-sdram --sdram-init boot.json --with-rvc  --with-privileged-debug --hardware-breakpoints 4 --jtag-tap --with-jtagremote

Terminal 2 :

cd openocd
src/openocd  -f ???/jtag_remote.cfg -f ???/riscv_jtag_tunneled.tcl 

jtag_remote.cfg and riscv_jtag_tunneled.tcl being openocd_scripts.zip.

You should get something like :

Open On-Chip Debugger 0.11.0+dev-04033-g058dfa50d (2023-11-27-14:31)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
DEPRECATED! use 'remote_bitbang host' not 'remote_bitbang_host'
DEPRECATED! use 'remote_bitbang port' not 'remote_bitbang_port'
Info : Simple Register based Bscan Tunnel Selected
Info : Initializing remote_bitbang driver
Info : Connecting to localhost:44853
Info : remote_bitbang driver initialized
Info : This adapter doesn't support configurable speed
Info : JTAG tap: riscv.cpu tap/device found: 0x10003fff (mfg: 0x7ff (<invalid>), part: 0x0003, ver: 0x1)
Info : [riscv.cpu.0] datacount=1 progbufsize=2
Info : Disabling abstract command reads from CSRs.
Info : [riscv.cpu.0] Examined RISC-V core; found 1 harts
Info : [riscv.cpu.0]  XLEN=32, misa=0x40041105
[riscv.cpu.0] Target successfully examined.
Info : starting gdb server for riscv.cpu.0 on 3333
Info : Listening on port 3333 for gdb connections
Ready for Remote Connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : accepting 'telnet' connection on tcp/4444

[enjoy-digital]

Thanks @Dolu1990 for the PR and instruction to use it!