add xcelium support

Makefile

@@ -180,6 +180,10 @@ vcs-sim:
 vcs-ams-sim:
 	$(FUSESOC) --cores-root . run --no-export --target=sim --flag "ams_sim" --tool=vcs $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
 
+## xcelium simulation
+xcelium-sim:
+	$(FUSESOC) --cores-root . run --no-export --target=sim --tool=xcelium $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
+
 ## Generates the build output for helloworld application
 ## Uses verilator to simulate the HW model and run the FW
 ## UART Dumping in uart0.log to show recollected results

README.md

@@ -275,7 +275,7 @@ Moreover, FreeRTOS is being fetch from 'https://github.com/FreeRTOS/FreeRTOS-Ker
 
 ## Simulating
 
-This project supports simulation with Verilator, Synopsys VCS, and Siemens Questasim.
+This project supports simulation with Verilator, Synopsys VCS, Siemens Questasim and Cadence Xcelium.
 It relies on `fusesoc` to handle multiple EDA tools and parameters.
 For example, if you want to set the `FPU` and `COREV_PULP` parameters of the `cv32e40p` CPU,
 you need to add next to your compilation command `FUSESOC_PARAM="--COREV_PULP=1 --FPU=1"`
@@ -400,6 +400,26 @@ make run RUN_OPT=1 RUN_UPF=1 PLUSARGS="c firmware=../../../sw/build/main.hex"
 
 Questasim version must be >= Questasim 2020.4
 
+### Compiling for Xcelium
+
+To simulate your application with Xcelium, first compile the HDL:
+
+```
+make xcelium-sim
+```
+
+then, go to your target system built folder
+
+```
+cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-xcelium/
+```
+
+and type to run your compiled software:
+
+```
+make run PLUSARGS="c firmware=../../../sw/build/main.hex"
+```
+
 ### UART DPI
 
 To simulate the UART, we use the LowRISC OpenTitan [UART DPI](https://github.com/lowRISC/opentitan/tree/master/hw/dv/dpi/uartdpi).

core-v-mini-mcu.core

@@ -313,20 +313,26 @@ targets:
     - tool_modelsim? (pre_patch_modelsim_Makefile)
     - tool_vcs? (cfile_uartdpi)
     - tool_vcs? (pre_build_remote_bitbang)
+    - tool_xcelium? (pre_build_remote_bitbang)
+    - tool_xcelium? (pre_build_uartdpi)
     - tool_verilator? (tb-verilator)
     - tool_modelsim? (tb-sv)
     - tool_vcs? (tb-sv)
+    - tool_xcelium? (tb-sv)
     - "!integrated_heep? (x_heep_system)"
     toplevel:
     - tool_modelsim? (tb_top)
     - tool_vcs? (tb_top)
+    - tool_xcelium? (tb_top)
     - tool_verilator? (testharness)
     hooks:
       pre_build:
         - tool_modelsim? (pre_build_uartdpi)
         - tool_modelsim? (pre_build_remote_bitbang)
         - tool_modelsim? (pre_patch_modelsim_Makefile) # this is required by Questa 2020 on
         - ams_sim? (pre_patch_vcs_ams_Makefile)
+        - tool_xcelium? (pre_build_uartdpi)
+        - tool_xcelium? (pre_build_remote_bitbang)
     parameters:
     - COREV_PULP
     - FPU
@@ -364,6 +370,12 @@ targets:
          - -LDFLAGS "-pthread -lutil"
          - +lint=TFIPC-L
          - -V
+      xcelium:
+        xrun_options:
+        - -vtimescale 1ns/10ps
+        - -sv_lib ../../../hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.so
+        - -sv_lib ../../../hw/vendor/pulp_platform_pulpissimo/rtl/tb/remote_bitbang/librbs.so
+        - -define XCELIUM
       verilator:
         mode: cc
         verilator_options:

hw/ip/i2s/rtl/i2s_core.sv

@@ -7,8 +7,8 @@
 // Description: I2s core logic 
 
 module i2s_core #(
-    parameter MaxWordWidth,
-    parameter ClkDividerWidth
+    parameter MaxWordWidth = 32,
+    parameter ClkDividerWidth = 8
 ) (
     input logic clk_i,
     input logic rst_ni,

hw/ip/i2s/rtl/i2s_ws_gen.sv

@@ -10,7 +10,7 @@
 // by Antonio Pullini (pullinia@iis.ee.ethz.ch)
 
 module i2s_ws_gen #(
-    parameter MaxWordWidth,
+    parameter MaxWordWidth = 32,
     localparam int unsigned CounterWidth = $clog2(MaxWordWidth)
 ) (
     input logic sck_i,

hw/vendor/lowrisc_opentitan/hw/dv/dpi/uartdpi/uartdpi.sv

@@ -84,11 +84,13 @@ module uartdpi #(
 
 `ifndef VCS
 `ifndef MODELSIM
+`ifndef XCELIUM
   initial begin
     // Prevent falling edges of rx_i before reset causing spurious characters
     seen_reset = 0;
   end
 `endif
+`endif
 `endif
 
   // RX

hw/vendor/patches/lowrisc_opentitan/uartdpi.patch

@@ -1,5 +1,5 @@
 diff --git a/hw/dv/dpi/uartdpi/uartdpi.h b/hw/dv/dpi/uartdpi/uartdpi.h
-index 29d50a5a2..2149fb115 100644
+index 29d50a5a28..2149fb1155 100644
 --- a/hw/dv/dpi/uartdpi/uartdpi.h
 +++ b/hw/dv/dpi/uartdpi/uartdpi.h
 @@ -5,7 +5,9 @@
@@ -21,21 +21,23 @@ index 29d50a5a2..2149fb115 100644
 +#endif
  #endif  // OPENTITAN_HW_DV_DPI_UARTDPI_UARTDPI_H_
 diff --git a/hw/dv/dpi/uartdpi/uartdpi.sv b/hw/dv/dpi/uartdpi/uartdpi.sv
-index 97fae4767..07c75cf8e 100644
+index 97fae47674..2be4df54ff 100644
 --- a/hw/dv/dpi/uartdpi/uartdpi.sv
 +++ b/hw/dv/dpi/uartdpi/uartdpi.sv
-@@ -82,11 +82,14 @@ module uartdpi #(
+@@ -82,11 +82,16 @@ module uartdpi #(
      end
    end
 
 -
 +`ifndef VCS
 +`ifndef MODELSIM
++`ifndef XCELIUM
    initial begin
      // Prevent falling edges of rx_i before reset causing spurious characters
      seen_reset = 0;
    end
 +`endif
++`endif
 +`endif
 
    // RX

hw/vendor/patches/pulp_platform_common_cells/clk_mux_glitch_free.patch

@@ -0,0 +1,13 @@
+diff --git a/src/clk_mux_glitch_free.sv b/src/clk_mux_glitch_free.sv
+index e0eb5cd..5193742 100644
+--- a/src/clk_mux_glitch_free.sv
++++ b/src/clk_mux_glitch_free.sv
+@@ -191,7 +191,7 @@ endmodule
+
+ // Helper Module to generate an N-input clock OR-gate from a tree of tc_clk_or2 cells.
+ module clk_or_tree #(
+-  parameter int unsigned NUM_INPUTS
++  parameter int unsigned NUM_INPUTS = 1
+ ) (
+   input logic [NUM_INPUTS-1:0] clks_i,
+   output logic clk_o

hw/vendor/patches/yosyshq_picorv32/0002-spiflash_valueargs.patch → hw/vendor/patches/yosyshq_picorv32/spiflash.patch

@@ -1,5 +1,5 @@
 diff --git a/picosoc/spiflash.v b/picosoc/spiflash.v
-index 22b337b..88582b3 100644
+index 22b337b..55342b5 100644
 --- a/picosoc/spiflash.v
 +++ b/picosoc/spiflash.v
 @@ -26,7 +26,7 @@
@@ -30,7 +30,7 @@ index 22b337b..88582b3 100644
  	initial begin
 -		if (!$value$plusargs("firmware=%s", firmware_file))
 +		for (i=0;i<=16*1024*1024;i=i+1)
-+			memory[i] = '0;
++			memory[i] = 8'h00;
 +		result = $value$plusargs("firmware=%s", firmware_file);
 +		if (!result)
  			firmware_file = "firmware.hex";

hw/vendor/pulp_platform_common_cells/src/clk_mux_glitch_free.sv

@@ -191,7 +191,7 @@ endmodule
 
 // Helper Module to generate an N-input clock OR-gate from a tree of tc_clk_or2 cells.
 module clk_or_tree #(
-  parameter int unsigned NUM_INPUTS
+  parameter int unsigned NUM_INPUTS = 1
 ) (
   input logic [NUM_INPUTS-1:0] clks_i,
   output logic clk_o

hw/vendor/yosyshq_picorv32/picosoc/spiflash.v

@@ -109,7 +109,7 @@ module spiflash (
 
 	initial begin
 		for (i=0;i<=16*1024*1024;i=i+1)
-			memory[i] = '0;
+			memory[i] = 8'h00;
 		result = $value$plusargs("firmware=%s", firmware_file);
 		if (!result)
 			firmware_file = "firmware.hex";

tb/tb_util.svh.tpl

@@ -96,7 +96,7 @@ endtask
 
 % for bank in range(ram_numbanks):
 task tb_writetoSram${bank};
-  input integer addr;
+  input int addr;
   input [7:0] val3;
   input [7:0] val2;
   input [7:0] val1;

x-heep-tb-utils.core

@@ -79,13 +79,17 @@ targets:
     - tool_verilator? (uartdpi)
     - tool_modelsim? (systemverilog_only_uart)
     - tool_vcs? (systemverilog_only_uart)
+    - tool_xcelium? (systemverilog_only_uart)
     - tool_verilator? (files_verilator_waiver)
     - tool_verilator? (remote_bitbang_dpi)
     - tool_modelsim? (systemverilog_only_simjtag)
     - tool_vcs? (systemverilog_only_simjtag)
+    - tool_xcelium? (systemverilog_only_simjtag)
     - tool_modelsim? (cypress_flash)
     - tool_vcs? (cypress_flash)
+    - tool_xcelium? (cypress_flash)
     toplevel:
     - tool_modelsim? (tb_top)
     - tool_vcs? (tb_top)
+    - tool_xcelium? (tb_top)
     - tool_verilator? (testharness)