Skip to content

Commit

Permalink
asm! support for the Xtensa architecture (#68)
Browse files Browse the repository at this point in the history
  • Loading branch information
@MabezDev
MabezDev committed May 16, 2023
1 parent f20b838 commit 2d73921
Show file tree
Hide file tree
Showing 6 changed files with 525 additions and 0 deletions.
8 changes: 8 additions & 0 deletions compiler/rustc_codegen_llvm/src/asm.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -240,6 +240,7 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
InlineAsmArch::S390x => {}
InlineAsmArch::SpirV => {}
InlineAsmArch::Wasm32 | InlineAsmArch::Wasm64 => {}
InlineAsmArch::Xtensa => {}
InlineAsmArch::Bpf => {}
InlineAsmArch::Msp430 => {
constraints.push("~{sr}".to_string());
Expand Down Expand Up @@ -661,6 +662,9 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'_>>) ->
| X86InlineAsmRegClass::tmm_reg,
) => unreachable!("clobber-only"),
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => "f",
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::breg) => "b",
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => "r",
Expand Down Expand Up @@ -716,6 +720,7 @@ fn modifier_to_llvm(
InlineAsmRegClass::Mips(_) => None,
InlineAsmRegClass::Nvptx(_) => None,
InlineAsmRegClass::PowerPC(_) => None,
InlineAsmRegClass::Xtensa(_) => None,
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
| InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::vreg) => {
Expand Down Expand Up @@ -829,6 +834,9 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
unreachable!("clobber-only")
}
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => cx.type_i32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => cx.type_f32(),
InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::breg) => cx.type_i1(),
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => cx.type_i8(),
Expand Down
31 changes: 31 additions & 0 deletions compiler/rustc_codegen_ssa/src/target_features.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -292,6 +292,35 @@ const WASM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
// tidy-alphabetical-end
];

const XTENSA_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("fp", Some(sym::xtensa_target_feature)),
("windowed", Some(sym::xtensa_target_feature)),
("bool", Some(sym::xtensa_target_feature)),
("loop", Some(sym::xtensa_target_feature)),
("sext", Some(sym::xtensa_target_feature)),
("nsa", Some(sym::xtensa_target_feature)),
("mul32", Some(sym::xtensa_target_feature)),
("mul32high", Some(sym::xtensa_target_feature)),
("div32", Some(sym::xtensa_target_feature)),
("mac16", Some(sym::xtensa_target_feature)),
("dfpaccel", Some(sym::xtensa_target_feature)),
("s32c1i", Some(sym::xtensa_target_feature)),
("threadptr", Some(sym::xtensa_target_feature)),
("extendedl32r", Some(sym::xtensa_target_feature)),
("atomctl", Some(sym::xtensa_target_feature)),
("memctl", Some(sym::xtensa_target_feature)),
("debug", Some(sym::xtensa_target_feature)),
("exception", Some(sym::xtensa_target_feature)),
("highpriinterrupts", Some(sym::xtensa_target_feature)),
("coprocessor", Some(sym::xtensa_target_feature)),
("interrupt", Some(sym::xtensa_target_feature)),
("rvector", Some(sym::xtensa_target_feature)),
("timerint", Some(sym::xtensa_target_feature)),
("prid", Some(sym::xtensa_target_feature)),
("regprotect", Some(sym::xtensa_target_feature)),
("miscsr", Some(sym::xtensa_target_feature)),
];

const BPF_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[("alu32", Some(sym::bpf_target_feature))];

/// When rustdoc is running, provide a list of all known features so that all their respective
Expand All @@ -308,6 +337,7 @@ pub fn all_known_features() -> impl Iterator<Item = (&'static str, Option<Symbol
.chain(MIPS_ALLOWED_FEATURES.iter())
.chain(RISCV_ALLOWED_FEATURES.iter())
.chain(WASM_ALLOWED_FEATURES.iter())
.chain(XTENSA_ALLOWED_FEATURES.iter())
.chain(BPF_ALLOWED_FEATURES.iter())
.cloned()
}
Expand All @@ -322,6 +352,7 @@ pub fn supported_target_features(sess: &Session) -> &'static [(&'static str, Opt
"powerpc" | "powerpc64" => POWERPC_ALLOWED_FEATURES,
"riscv32" | "riscv64" => RISCV_ALLOWED_FEATURES,
"wasm32" | "wasm64" => WASM_ALLOWED_FEATURES,
"xtensa" => XTENSA_ALLOWED_FEATURES,
"bpf" => BPF_ALLOWED_FEATURES,
_ => &[],
}
Expand Down
23 changes: 23 additions & 0 deletions compiler/rustc_span/src/symbol.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -395,6 +395,7 @@ symbols! {
async_await,
async_closure,
async_fn_in_trait,
atomctl,
atomic,
atomic_mod,
atomics,
Expand Down Expand Up @@ -435,6 +436,7 @@ symbols! {
braced_empty_structs,
branch,
breakpoint,
breg,
bridge,
bswap,
c_str,
Expand Down Expand Up @@ -538,7 +540,10 @@ symbols! {
const_try,
constant,
constructor,
contents,
context,
convert,
coprocessor,
copy,
copy_closures,
copy_nonoverlapping,
Expand Down Expand Up @@ -608,6 +613,7 @@ symbols! {
derive_default_enum,
destruct,
destructuring_assignment,
dfpaccel,
diagnostic,
direct,
discriminant_kind,
Expand Down Expand Up @@ -663,6 +669,7 @@ symbols! {
ermsb_target_feature,
exact_div,
except,
exception,
exchange_malloc,
exclusive_range_pattern,
exhaustive_integer_patterns,
Expand All @@ -679,6 +686,7 @@ symbols! {
expr,
extended_key_value_attributes,
extended_varargs_abi_support,
extendedl32r,
extern_absolute_paths,
extern_crate_item_prelude,
extern_crate_self,
Expand Down Expand Up @@ -735,6 +743,7 @@ symbols! {
format_macro,
format_placeholder,
format_unsafe_arg,
fp,
freeze,
freg,
frem_fast,
Expand Down Expand Up @@ -776,6 +785,7 @@ symbols! {
hash,
hexagon_target_feature,
hidden,
highpriinterrupts,
homogeneous_aggregate,
html_favicon_url,
html_logo_url,
Expand Down Expand Up @@ -827,6 +837,8 @@ symbols! {
instruction_set,
integer_: "integer",
integral,
intel,
interrupt,
into_future,
into_iter,
intra_doc_pointers,
Expand Down Expand Up @@ -889,6 +901,7 @@ symbols! {
logf64,
loop_break_value,
lt,
mac16,
macro_at_most_once_rep,
macro_attributes_in_derive_output,
macro_escape,
Expand Down Expand Up @@ -927,6 +940,7 @@ symbols! {
mem_variant_count,
mem_zeroed,
member_constraints,
memctl,
memory,
memtag,
message,
Expand All @@ -944,6 +958,7 @@ symbols! {
mips_target_feature,
miri,
misc,
miscsr,
mmx_reg,
modifiers,
module,
Expand Down Expand Up @@ -1108,6 +1123,7 @@ symbols! {
prelude,
prelude_import,
preserves_flags,
prid,
primitive,
print_macro,
println_macro,
Expand Down Expand Up @@ -1301,7 +1317,9 @@ symbols! {
rustdoc_missing_doc_code_examples,
rustfmt,
rvalue_static_promotion,
rvector,
s,
s32c1i,
safety,
sanitize,
sanitizer_runtime,
Expand Down Expand Up @@ -1473,8 +1491,10 @@ symbols! {
thread,
thread_local,
thread_local_macro,
threadptr,
thumb2,
thumb_mode: "thumb-mode",
timerint,
tmm_reg,
to_string,
to_vec,
Expand Down Expand Up @@ -1607,6 +1627,7 @@ symbols! {
wasm_target_feature,
while_let,
width,
windowed,
windows,
windows_subsystem,
with_negative_coherence,
Expand All @@ -1620,7 +1641,9 @@ symbols! {
writeln_macro,
x87_reg,
xer,
xloop,
xmm_reg,
xtensa_target_feature,
yeet_desugar_details,
yeet_expr,
ymm_reg,
Expand Down
Loading

0 comments on commit 2d73921

Please sign in to comment.