Xtensa asm! implementation

[MabezDev]

Status

Mostly working but a few oddities. @KerryRJ kindly provided ports for the asm in the xtensa-lx & xtensa-lx so we know the core use case is solved.

However there are a few things left to do.

TODO

• Class based register allocation - bug in llvm backend - moved to Verify floating point inline asm register allocation works #69
• f64 allocation with the dpacell feature?
• fix TODO's surrounding feature support
• Documentation

[KerryRJ]

Where is this assembly?

[MabezDev]

Where is this assembly?

Just some random asm I created to test the feature gating of the registers. I don't think this will stop us from implementing xtensa-lx-rt or anything.

[KerryRJ]

xtensa-lx-rt builds fine but I'm getting the same errors on xtensa-lx.

[MabezDev]

@KerryRJ I see you have ported the asm in xtensa-lx, would you mind PR'ing that?

Are you porting xtensa-lx-rt as well or should I take a look?

[KerryRJ]

Both are ported. Busy trying to figure why xtensa-lx is failing.

[MabezDev]

Both are ported. Busy trying to figure why xtensa-lx is failing.

I tried it and I don't think there is an issue, just running cargo build in xtensa-lx errors because the target is not set to xtensa via .cargo/config, which results in errors like this:

error: invalid register `a0`: unknown register
  --> src/lib.rs:37:24
   |
37 |         in(reg) stack, out("a0") _, options(nostack)
   |                        ^^^^^^^^^^^

error: invalid register `a0`: unknown register
  --> src/lib.rs:54:41
   |
54 |             ", out(reg) x, out(reg) _y, out("a0") _, options(nostack))
   |                                         ^^^^^^^^^^^

error: could not compile `xtensa-lx` due to 2 previous errors

My machine is x86 hence a0 is an unknown register.

Building using cargo +esp-dev build --target xtensa-esp32-none-elf -Zbuild-std=core results in sucessfull compilation.

I fell into a similar trap earlier today, it turns outs only input/output registers are validated on the rust side (source: https://rust-lang.zulipchat.com/#narrow/stream/182449-t-compiler.2Fhelp/topic/asm!.20register.20filter/near/248466515), hence why it only failed on those select few functions where we had to mark a0 as clobbered.

If that was your issue would you mind PR'ing both your xtensa-lx & xtensa-lx-rt changes?

[KerryRJ]

I can't believe I tripped over that again and wasted so much time! Completely forgot about the target as I usually add a config.toml to the builds so that I don't have to pass them on the command line. Good catch!

Getting a lot of these now when using cargo build --target xtensa-esp32-none-elf -Zbuild-std=core

'+memctl' is not a recognized feature for this target (ignoring feature)

I will PR both of them.

[MabezDev]

'+memctl' is not a recognized feature for this target (ignoring feature)

Nothing to worry about, it's a small typo in the llvm fork: espressif/llvm-project#47

I will PR both of them.

Thank you!

[KerryRJ]

I have just tried the following snippet in the xtensa-rust-quickstart and it is building without any problems:-

    let o: u32;
    unsafe {
        asm!(
            "mov {0}, {1}",
            "add {0}, {number}",
            out(reg) o,
            in(reg) i,
            number = const 5,
        );
    }
    assert_eq!(o, 8);

    let _x: f32;
    unsafe {
        asm!(
            "lsi {}, a0, 152", out(freg) _x
        );
    };`

Additional TODOs to consider?

- Update documentation.

- Add types tests.

[MabezDev]

unsafe {
    asm!(
        "mov {0}, {1}",
        "add {0}, {number}",
        out(reg) o,
        in(reg) i,
        number = const 5,
    );
}

This is not valid Xtensa assembly, what target are you building for? It should look like this instead:

unsafe {
  asm!(
    "mov {0}, {1}",
    "addi {0}, {0}, {number}",
    out(reg) o,
    in(reg) i,
    number = const 5,
  );
}