tcl/espressif: refactor jtag and target create scripts

espressif · Jul 18, 2024 · 4dae77e · 4dae77e
1 parent 47af42f
commit 4dae77e
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Showing 10 changed files with 139 additions and 163 deletions.
diff --git a/tcl/target/esp32.cfg b/tcl/target/esp32.cfg
@@ -6,15 +6,16 @@ source [find target/esp_common.cfg]
 
 # Target specific global variables
 set _CHIPNAME "esp32"
+set _CHIP_HP_NAME $_CHIPNAME
 set _CPUTAPID 0x120034e5
+set _HP_TAPNUM 2
 set _ESP_ARCH "xtensa"
 set _ESP_SMP_TARGET 1
-set _ESP_SMP_BREAK 1
 set _ESP_EFUSE_MAC_ADDR_REG 0x3ff5A004
 
 # if not set until now, set as default dual core
 if { ![info exists _ONLYCPU] } {
- set _ONLYCPU 3
+ set _ONLYCPU 0x03
 }
 
 set _FLASH_VOLTAGE 3.3

diff --git a/tcl/target/esp32c2.cfg b/tcl/target/esp32c2.cfg
@@ -6,11 +6,11 @@ source [find target/esp_common.cfg]
 
 # Target specific global variables
 set _CHIPNAME "esp32c2"
+set _CHIP_HP_NAME $_CHIPNAME
 set _CPUTAPID 0x0000cc25
 set _ESP_ARCH "riscv"
-set _ONLYCPU 1
-set _ESP_SMP_TARGET 0
-set _ESP_SMP_BREAK 0
+set _ONLYCPU 0x01
+set _HP_TAPNUM 1
 set _ESP_EFUSE_MAC_ADDR_REG 0x60008840
 
 # Set workarea address and size
@@ -48,7 +48,7 @@ proc esp32c2_soc_reset { } {
  # all the peripherals except for the RTC block.
  # It is called from reset-assert-post target event callback,
  # after assert_reset procedure was called.
- # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
+ # Since we need the hart to execute a write to RTC_CNTL_SW_SYS_RST,
  # temporarily take it out of reset. Save the dmcontrol state before
  # doing so.
  riscv dmi_write $_RISCV_DMCONTROL 0x80000001

diff --git a/tcl/target/esp32c3.cfg b/tcl/target/esp32c3.cfg
@@ -6,11 +6,11 @@ source [find target/esp_common.cfg]
 
 # Target specific global variables
 set _CHIPNAME "esp32c3"
+set _CHIP_HP_NAME $_CHIPNAME
 set _CPUTAPID 0x00005c25
 set _ESP_ARCH "riscv"
-set _ONLYCPU 1
-set _ESP_SMP_TARGET 0
-set _ESP_SMP_BREAK 0
+set _ONLYCPU 0x01
+set _HP_TAPNUM 1
 set _ESP_EFUSE_MAC_ADDR_REG 0x60008844
 
 # Set workarea address and size
@@ -50,7 +50,7 @@ proc esp32c3_soc_reset { } {
  # all the peripherals except for the RTC block.
  # It is called from reset-assert-post target event callback,
  # after assert_reset procedure was called.
- # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
+ # Since we need the hart to execute a write to RTC_CNTL_SW_SYS_RST,
  # temporarily take it out of reset. Save the dmcontrol state before
  # doing so.
  riscv dmi_write $_RISCV_DMCONTROL 0x80000001

diff --git a/tcl/target/esp32c5.cfg b/tcl/target/esp32c5.cfg
@@ -7,11 +7,13 @@ source [find target/esp_common.cfg]
 
 # Target specific global variables
 set _CHIPNAME "esp32c5"
+set _CHIP_LP_NAME $_CHIPNAME.lp
+set _CHIP_HP_NAME $_CHIPNAME.hp
 set _CPUTAPID 0x00017c25
 set _ESP_ARCH "riscv"
-set _ONLYCPU 2
-set _ESP_SMP_TARGET 0
-set _ESP_SMP_BREAK 0
+set _ONLYCPU 0x01
+set _LP_TAPNUM  1
+set _HP_TAPNUM  1
 set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844
 
 # Set workarea address and size

diff --git a/tcl/target/esp32c6.cfg b/tcl/target/esp32c6.cfg
@@ -6,11 +6,13 @@ source [find target/esp_common.cfg]
 
 # Target specific global variables
 set _CHIPNAME "esp32c6"
+set _CHIP_LP_NAME $_CHIPNAME.lp
+set _CHIP_HP_NAME $_CHIPNAME.hp
 set _CPUTAPID 0x0000dc25
 set _ESP_ARCH "riscv"
-set _ONLYCPU 1
-set _ESP_SMP_TARGET 0
-set _ESP_SMP_BREAK 0
+set _ONLYCPU 0x01
+set _LP_TAPNUM  1
+set _HP_TAPNUM  0
 set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844
 
 # Set workarea address and size

diff --git a/tcl/target/esp32h2.cfg b/tcl/target/esp32h2.cfg
@@ -7,10 +7,11 @@ source [find target/esp_common.cfg]
 # Target specific global variables
 set _CHIPNAME "esp32h2"
 set _CPUTAPID 0x00010c25
+set _CHIP_LP_NAME $_CHIPNAME.lp
+set _CHIP_HP_NAME $_CHIPNAME.hp
 set _ESP_ARCH "riscv"
-set _ONLYCPU 1
-set _ESP_SMP_TARGET 0
-set _ESP_SMP_BREAK 0
+set _ONLYCPU 0x01
+set _HP_TAPNUM 1
 set _ESP_EFUSE_MAC_ADDR_REG 0x600B0844
 
 # Set workarea address and size

diff --git a/tcl/target/esp32p4.cfg b/tcl/target/esp32p4.cfg
@@ -6,13 +6,14 @@ source [find target/esp_common.cfg]
 
 # Target specific global variables
 set _CHIPNAME "esp32p4"
-set _CHIP_HP_NAME $_CHIPNAME.hp
 set _CHIP_LP_NAME $_CHIPNAME.lp
+set _CHIP_HP_NAME $_CHIPNAME.hp
 set _CPUTAPID 0x0012c25
 set _ESP_ARCH "riscv"
-set _ONLYCPU 3
+set _ONLYCPU 0x03
+set _LP_TAPNUM 1
+set _HP_TAPNUM 1
 set _ESP_SMP_TARGET 1
-set _ESP_SMP_BREAK 0
 set _ESP_EFUSE_MAC_ADDR_REG 0x5012D044
 set _RTOS "FreeRTOS"
 
@@ -93,76 +94,13 @@ proc esp32p4_memprot_is_enabled { } {
  return 0
 }
 
-proc set_esp32p4_variables { } {
- global _CHIPNAME _CHIP_LP_NAME _CHIP_HP_NAME
- global _CPUNAME _CPUNAME_0 _CPUNAME_1
- global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1
- global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED
-
- # There are 2 jtag taps with daisy chain connection. tap0 connected to lp core, tap1 connected to dual hp core
- # For now we support only hp core debugging. OCD-772 for the LP Core debugging on C6 and P4
- set _CPUNAME cpu
- set _CPUNAME0 cpu0
- set _CPUNAME1 cpu1
- set _TARGETNAME_0 $_CHIP_HP_NAME.$_CPUNAME0
- set _TARGETNAME_1 $_CHIP_HP_NAME.$_CPUNAME1
- set _TAPNAME_0 $_CHIP_HP_NAME.$_CPUNAME
- set _TAPNAME_1 $_CHIP_HP_NAME.$_CPUNAME
-
- set _ESP_WDT_DISABLE "${_CHIPNAME}_cpu0_wdt_disable"
- set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset"
- set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled"
-}
-
 proc create_esp32p4_jtag { } {
  global _CHIP_LP_NAME _CHIP_HP_NAME _CPUNAME _CPUTAPID
  jtag newtap $_CHIP_LP_NAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
  jtag newtap $_CHIP_HP_NAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
 }
 
-proc configure_esp32p4_event_reset_assert_post { } {
- global _TARGETNAME_0
-
- $_TARGETNAME_0 configure -event reset-assert-post {
- esp32p4_soc_reset
- }
-}
-
-proc configure_esp32p4_event_halted { } {
- global _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU
-
- if {$_ONLYCPU & 1} {
- $_TARGETNAME_0 configure -event halted {
- global _ESP_WDT_DISABLE
- $_ESP_WDT_DISABLE
- esp halted_event_handler
- }
- }
- if {$_ONLYCPU & 2} {
- $_TARGETNAME_1 configure -event halted {
- esp halted_event_handler
- }
- }
-}
-
-proc configure_esp32p4_openocd_events { } {
- configure_esp32p4_event_halted
- configure_shutdown_command
- configure_event_examine_end
- configure_esp32p4_event_reset_assert_post
- configure_event_gdb_attach
-}
-
-proc create_esp32p4_target { } {
- set_esp32p4_variables
- create_esp32p4_jtag
- create_openocd_targets
- configure_esp_flash_settings
- configure_esp32p4_openocd_events
- configure_esp_riscv_default_settings
-}
-
-create_esp32p4_target
+create_esp_target $_ESP_ARCH
 
 foreach tgt [target names] {
  $tgt riscv expose_csrs 848=mclicbase

diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg
@@ -6,11 +6,11 @@ source [find target/esp_common.cfg]
 
 # Target specific global variables
 set _CHIPNAME "esp32s2"
+set _CHIP_HP_NAME $_CHIPNAME
 set _CPUTAPID 0x120034e5
 set _ESP_ARCH "xtensa"
-set _ONLYCPU 1
-set _ESP_SMP_TARGET 0
-set _ESP_SMP_BREAK 1
+set _ONLYCPU 0x01
+set _HP_TAPNUM 1
 set _ESP_EFUSE_MAC_ADDR_REG 0x3f41A004
 
 # Set workarea address and size

diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
@@ -6,10 +6,11 @@ source [find target/esp_common.cfg]
 
 # Target specific global variables
 set _CHIPNAME "esp32s3"
+set _CHIP_HP_NAME $_CHIPNAME
 set _CPUTAPID 0x120034e5
+set _HP_TAPNUM 2
 set _ESP_ARCH "xtensa"
 set _ESP_SMP_TARGET 1
-set _ESP_SMP_BREAK 1
 set _ESP_EFUSE_MAC_ADDR_REG 0x60007044
 
 # if not set until now, set as default dual core