Development of a SoC for testing an IP Core. The project has been developped in VHDL, using Xilinx ISE and IP Core. In order to test the correct functionalities(simulation in presence of faults and without faults), it has been added a modified module to simulate fault simulation.
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Development of a SoC for testing an IP Core. The project has been developped in VHDL, using Xilinx ISE and IP Core. In order to test the correct functionalities(simulation in presence of faults and without faults), it has been added a modified module to simulate fault simulation.
florix/BIST_IP_CORE
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Development of a SoC for testing an IP Core. The project has been developped in VHDL, using Xilinx ISE and IP Core. In order to test the correct functionalities(simulation in presence of faults and without faults), it has been added a modified module to simulate fault simulation.
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