fix uart baudrate issue #3

fm4dd · Oct 6, 2024 · c84cc2a · c84cc2a
1 parent 43b5762
commit c84cc2a
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Showing 2 changed files with 6 additions and 3 deletions.
diff --git a/config.mk b/config.mk
@@ -7,7 +7,10 @@
 ## toolchain
 YOSYS = /home/fm/cc-toolchain-linux/bin/yosys/yosys
 PR    = /home/fm/cc-toolchain-linux/bin/p_r/p_r
-OFL   = /home/fm/cc-toolchain-linux/bin/openFPGALoader/openFPGALoader
+# disable CC-provided openFPGALoader, switch to "OSS CAD Suite" version
+# see https://github.com/fm4dd/gatemate-riscv/issues/5
+#OFL   = /home/fm/cc-toolchain-linux/bin/openFPGALoader/openFPGALoader
+OFL   = /home/fm/oss-cad-suite/bin/openFPGALoader
 
 GTKW = gtkwave
 IVL  = iverilog

diff --git a/rtl-shared/emmitter_uart.v b/rtl-shared/emmitter_uart.v
@@ -11,9 +11,9 @@ module corescore_emitter_uart
    output wire 	    o_uart_tx
 );
 
-   localparam START_VALUE = clk_freq_hz/baud_rate;
+   localparam START_VALUE = (clk_freq_hz/baud_rate)-2;
 
-   localparam WIDTH = $clog2(START_VALUE);
+   localparam WIDTH = $clog2(START_VALUE+2);
 
    reg [WIDTH:0]  cnt = 0;