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Fixes typo in verilog model so it matches the schematics #21

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Fixes typo in verilog model so it matches the schematics #21

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jotego
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@jotego jotego commented Aug 12, 2023

This typo fix will make the L1 signal match the schematic:

imagen

The inverted REG11[5] is used in the upper NAND gate

furrtek
furrtek approved these changes Nov 21, 2023
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Thank you !

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@furrtek furrtek furrtek approved these changes

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