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Fixes typo in verilog model so it matches the schematics #21

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Fixes typo in verilog model so it matches the schematics #21

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49ad776
Fixes typo in verilog model so it matches the schematics
jotego Aug 12, 2023
b2784d5
Merge branch 'furrtek:master' into master
jotego Nov 21, 2023
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24 changes: 12 additions & 12 deletions Konami/053251/053251.v
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ module k053251(

input [1:0] SDI,
output reg [1:0] SDO,

output reg [10:0] CO,
output reg BRIT,
output reg NCOL
Expand Down Expand Up @@ -129,7 +129,7 @@ wire J122A = (PR0PR1PR2PR3PR4MIX < ~REG5);
wire SELSHA = (PR0PR1PR2PR3PR4MIX < PRSHA);

// No need for L0 signal
wire L1 = ~(SEL_W2 & REG11[5]) & ~(~SEL_L1 & REG11[5]);
wire L1 = ~(SEL_W2 & REG11[5]) & ~(~SEL_L1 & ~REG11[5]);

wire [5:0] PR0MUX = TRANSP0 ? (REG12[0] ? REG0 : PR0_Q) : 6'h3F; // To check: gating
wire [5:0] PR1MUX = TRANSP1 ? (REG12[1] ? REG1 : PR1_Q) : 6'h3F; // To check: gating
Expand Down Expand Up @@ -180,37 +180,37 @@ always @(posedge CLK) begin
PR0_Q <= PR0;
PR1_Q <= PR1;
PR2_Q <= PR2;

TRANSP0_W1 <= TRANSP0;
TRANSP1_W1 <= TRANSP1;
TRANSP2_W1 <= TRANSP2;
TRANSP4_W1 <= TRANSP4;

L0L1L2MIX_Q <= L0L1L2MIX;
T0T1T2MIX_Q <= T0T1T2MIX;

L0L1L2L3MIX_Q <= L0L1L2L3MIX;
T0T1T2T3MIX_Q <= T0T1T2T3MIX;

CO <= L0L1L2L3L4MIX;
NCOL <= T0T1T2T3T4MIX;

PR2_W1 <= PR2MUX;
PR4_W1 <= PR4;

SEL_W1 <= SEL;
SEL_W2 <= SEL_W1;

PR0MUX_Q <= PR0MUX;
PR1MUX_Q <= PR1MUX;

PR0PR1PR2MIX_Q <= PR0PR1PR2MIX;
PR0PR1PR2PR3MIX_Q <= PR0PR1PR2PR3MIX;

SEL_L1 <= A49;
SEL_L4 <= G93;
BRIT <= J122A;

SDI_Q <= SDI;
SDI_W1 <= SDI_Q;
SDI_W2 <= SDI_W1;
Expand Down