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presets: add total cache presets for Zen4 CPUs
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Add preset definitions for total L2 total cache hits and misses.

These changes have been tested on the AMD Zen4 architecture using the
Counter Analysis Toolkit.
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@dbarry9 @gcongiu
dbarry9 authored and gcongiu committed Dec 15, 2023
1 parent ecd10c6 commit 3fb5494
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2 changes: 2 additions & 0 deletions src/papi_events.csv
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Original file line number Diff line number Diff line change
Expand Up @@ -544,6 +544,8 @@ PRESET,PAPI_L2_ICR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ:L2_HW_PF
PRESET,PAPI_L2_ICM,DERIVED_SUB,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S
PRESET,PAPI_L2_TCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C_S:LS_RD_BLK_L_HIT_X:LS_RD_BLK_L_HIT_S:LS_RD_BLK_X:IC_FILL_HIT_X:IC_FILL_HIT_S
PRESET,PAPI_L2_TCM,DERIVED_ADD,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS


CPU,Intel architectural PMU
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